Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Phansco Co., Ltd.

Cheng-Chien Li

Chi-Wen Liu

Hsin-Chieh Huang

Chia-Ming Chang

Yao-Chun Chuang

Ching-Pin Lin

Min-Feng Ku

Wei-Chih Lin

Song-Bor Lee

Wei-Chung Chao

Ching-Kun Huang

Ching-Wei Yu

Chao-Ming Tsen

Yung-Hsiang Wang

Shih-Chang Chen

Wei-Shuo Ho

Yu-Ching Huang

Wen-Li Chiu

Kun-Hsiang Lin

Shao-Kai Lin

Huang-Chao Chang

Tzu-Hung Hsu

Chang-Jung Wen

Wei-Zhe Jhang

Pin-Hsuan Yeh

Chun-Yu Chuang

Integrated circuit (IC) structures and methods for forming the same are provided. An IC structure according to the present disclosure includes a substrate, an interconnect structure over the substrate, a guard ring structure disposed in the interconnect structure, a via structure vertically extending through the guard ring structure, and a top metal feature disposed directly over and in contact with the guard ring structure and the via structure. The guard ring structure includes a plurality of guard ring layers. Each of the plurality of guard ring layers includes a lower portion and an upper portion disposed over the lower portion. Sidewalls of the lower portions and upper portions of the plurality of guard ring layers facing toward the via structure are substantially vertically aligned to form a smooth inner surface of the guard ring structure.

Guard ring structure

An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.

Through via structure

A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

Semiconductor device and method of forming the same

The present disclosure describes a semiconductor structure including a TSV in contact with a substrate and a metal ring structure laterally surrounding the TSV. The metal ring structure includes one or more metal rings arranged as a stack and one or more metal vias interposed between two adjacent metal rings of the one or more metal rings. The metal ring structure is electrically coupled to the substrate through one or more conductive structures.

Grounded metal ring structure for through-silicon via

A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.

Devices with through silicon vias, guard rings and methods of making the same

A method for detecting dust mite antigens includes the steps of collecting a dust sample, applying an extraction and cleanup procedure for dust mite antigens from the dust sample in order to obtain a sample solution ready for measurement, and placing the sample solution on a SERS chip without immunological modification and under a Raman spectrometer for SERS detection in order to identify whether any dust mite antigens exist in the sample solution.

System and method for detection of dust mite antigens

A surface-enhanced Raman scattering (SERS) detection method is provided for detecting a target analyte in a sample. The SERS detection method generally includes the steps of: (a). preparing an extract of the sample; (b). introducing the sample extract onto a SERS substrate, causing the target analyte to be absorbed in the SERS substrate; (c). introducing a volatile organic solvent onto the SERS substrate to have the target analyte of the sample extract dissolved and comes out of the SERS substrate; (d). irradiating the SERS substrate with light to evaporate the volatile organic solvent, leaving a more condensed target analyte on the SERS substrate; (e). irradiating the condensed target analyte with laser light to have the target analyte penetrate deeply into the SERS substrate; and (f). performing Raman measurement with a laser beam focusing on the SERS substrate to analyze the target analyte.

Surface-enhanced Raman scattering detection method for rapid detection of pesticide residues

A method for forming a FinFET device is described. The method includes the following steps. A substrate is patterned to form fins. Dummy gate stack is formed on the substrate and over the fins, wherein the dummy gate stack may be formed by the following steps: a dummy layer is formed; a first etching step is performed on the dummy layer with a bromine containing etching gas to form a dummy strip; a second etching step is performed on the dummy strip with a chlorine containing etching gas to form the dummy gate stack. The dummy gate stack is replaced with a gate stack.

FinFET devices having gate stacks with protruding parts and method of forming the same

Provided is a semiconductor device including a first fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure over a first semiconductor fin and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer has a bar-shaped structure, the second layer has a U-shaped structure encapsulating sidewalls and a bottom surface of the first layer, and the first layer and the second layer include different materials. A method of manufacturing the semiconductor device is also provided.

Semiconductor device having FinFET with work function layers and method of manufacturing the same

A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. A topmost location of the epitaxy structure has an n-type impurity concentration lower than an n-type impurity concentration of a location of the epitaxy structure below the topmost location.

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Jhubei, Taiwan

Cheng-Chien Li