United Microelectronics Corp.

United Silicon Incorporated

Cheng-Chieh Huang

Tse-Wei Liu

Tang Yu

Li-Wu Tsao

Cheng-Chih Kung

Terry Chung-Yi Chen

Eddie Chen

Da-Wen Hsia

Tzung-Hua Ying

Tommy Yu

A silicon oxide layer is formed on a semiconductor wafer by performing a high temperature oxidation (HTO) process using dichlorosilane (SiH Cl ) and nitrous oxide (N O), as reacting gases, having a flow rates with a ratio greater than 2:1, respectively. The reacting moles of dichlorosilane to nitrous oxide are in the proportion of 1:2.

Method of forming a silicon oxide layer

A method of increasing the selectivity of silicon nitride deposition. A substrate is provided. A silicon oxide layer is formed over a portion of the substrate. Ammonia NH is passed over the silicon oxide layer and the substrate surface for a definite period to perform a surface treatment. Silicon nitride is subsequently deposited over the substrate and the silicon oxide layer.

Method of increasing selectivity in silicon nitride deposition

A method for upgrading qualities of DRAM capacitors and wafer-to-wafer uniformity is disclosed. In order to effectively prevent wafers from contaminations, the invention uses an additional silane purge process in situ before performing a SHSG seeding process on the wafers. The silane purge process of this invention utilizes the original silane seeding gas inlet. In this manner, not only thicknesses and surface areas of the SHSG seeds and capacitances of DRAMs can be increased, but also wafer-to-wafer uniformity can be upgraded.

Method for upgrading quality of DRAM capacitor and wafer-to-wafer uniformity

A method for forming a capacitor containing selective hemispherical grained (S-HSG) polysilicon is disclosed. In this invention, dopant implantation is incorporated after the S-HSG growth to replace conventional wet clean procedure. The elimination of the cleaning treatments avoids the incidents of residue particles (due to cleaning) and minimizes numerous structure defects. The incorporation of the ion implantation technique would make up the insufficiency of doping requirement by applying in-diffusion alone. The combination of the in-diffusion and the implantation for doping procedure could maintain the device with good capacitance level even though the pre-clean procedure is excluded.

Method for forming a capacitor having selective hemispherical grained polysilicon

A method for cleaning a semiconductor wafer which includes the sequential steps of cleaning the wafer in a dilute hydrofluoric acid bath, cleaning the wafer in a first ozone bath, cleaning the wafer in a dilute hydrofluoric acid/hydrogen peroxide/hydrogen chloride bath, followed by cleaning the wafer in a second ozone bath. The method uses the dilute hydrofluoric acid/hydrogen peroxide/hydrochloric acid bath instead of the conventional DHF bath and RCA2 bath. Hence, the amount of chemicals consumed and the number of baths used by the cleaning station are lowered. In addition, ozone is passed into an overflow loath so that the highly reactive ozone can be utilized to clean the wafer without putting additional load on the cleaning station. Therefore, the cleaning operation can be carried out in a smaller cleaning station using somewhat lower temperature and lower concentration chemical solutions. The efficiency is as high as a multi-bath station, but chemicals are not wasted. Furthermore, the throughput is high and stable without causing too many safety and environmental problems.

Method for cleaning a semiconductor wafer

A method of water mark inspection. By forming a pattern on a test wafer, the water mark formed thereon directly reflects the features of a wafer product to be evaluated. The water mark is formed by simulating fabrication process conditions of forming the wafer product of which the performance is to be evaluated. Thus, after scanning the water mark by a defect inspection machine, the performance of the wafer product is evaluated.

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Hsin-Chu Hsien, Taiwan

Cheng-Chieh Huang