Taiwan Semiconductor Manufacturing Comp. Ltd.

Cheng-Cheng Kuo

Ming Zhu

Harry-Hak-Lay Chuang

Hua-Tai Lin

Ching-Che Tsai

Chi-Wen Liu

Kuei-Shun Chen

Jeng-Shiun Ho

Chih-Wei Hsu

Bao-Ru Young

Chia-Ping Chiang

Tzu-Chun Lo

Tsai-Sheng Gau

Hak-Lay Chuang

Yuan-Hsiang Lung

Yan-Tso Tsai

Yun-Lin Wu

Min-Hung Cheng

Ru-Gun Liu

Wen-Chun Huang

Chia-Chu Liu

Hsiao-Wei Su

Kong-Beng Thei

Hsin-Chang Lee

Ming-Hsing Tsai

Harry Chuang

Harry Hak-Lay Chuang

Kuei Shun Chen

Jye-Yen Cheng

Ken-Yu Chang

Chih-Hsiang Yao

Ming-Hui Chih

Yu-Po Tang

Chih-Shiang Chou

Cheng-Lung Tsai

Cheng-Kun Tsai

Shang-Yu Huang

Wei-Long Wang

Yu-Hsiang Lin

Bing-Syun Yeh

Josh J H Feng

Luke Lo

Chia-Wei Huang

Wei-Jhih Wang

Yuan-yao Chang

Ting-Chun Liu

Jing-Wei Shih

Wen-Han Chu

Harry-Hay-Lay Chuang

The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch, a second switch, and a third switch. The first switch has a first node coupled to a first device-under-test and a second node coupled to a first signal supply node. The second switch has a first node coupled to the second DUT and a second node coupled to the first signal supply node. The third switch has a first node directly coupled to the first DUT and the second DUT. The third switch has a second node coupled to a second signal supply node. The third switch selectively couples both of the first DUT and the second DUT to the second signal supply node.

Test circuit and method for operating the same

A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.

Vertical tunneling field-effect transistor cell

A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

Method for improving circuit layout for manufacturability

Vertical tunneling field-effect transistor cell and fabricating the same

Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.

A method for forming a tunneling field-effect transistor (TFET) is disclosed. The method includes etching a semiconductor substrate to form a semiconductor protrusion that protrudes out from a top surface of the semiconductor substrate, forming a drain region in lower portion of the semiconductor protrusion, and patterning a gate stack layer to form a gate stack. The gate stack has a gating surface that directly contacts and wraps around a middle portion of the semiconductor protrusion. The method further includes forming a source region in an upper portion of the semiconductor protrusion and forming a source contact over the source region, the source contact have a first width that is larger than a width of the source region.

A semiconductor die comprises two or more active regions over a substrate. A first set of dummy blocks are over the substrate, in contact with one another, and completely surrounding at least one of the two or more active regions. A second set of dummy blocks are over the substrate and farther from the at least one active region surrounded by the first set of dummy blocks than the dummy blocks of the first set of dummy blocks. Each of the dummy blocks of the first set of dummy blocks has individual surface areas, each of the dummy blocks of the second set of dummy blocks has individual surface areas, and the individual surface areas of each of the dummy blocks of the second set of dummy blocks is larger than the individual surface areas of each of the dummy blocks of the first set of dummy blocks.

Metal gate features of semiconductor die

A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack.

A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.

Method for removing semiconductor fins using alternating masks

The present disclosure provides a semiconductor device. A first active region is formed in a substrate. The first active region is elongated in a first direction in a top view. A first gate is formed over the substrate. The first gate is elongated in a second direction in the top view. A portion of the first gate is located over the first active region. A second gate is formed over the substrate. The second gate is elongated in the second direction in the top view. A portion of the second gate is located over the first active region. The second gate is shorter than the first gate in the second direction.

N/P boundary effect reduction for metal gate transistors

A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over a substrate and protruding out of the plane of substrate. A source region is disposed as a top portion of the frustoconical protrusion structure. A sidewall spacer is disposed along sidewall of the source region. A source contact with a critical dimension (CD), which is substantially larger than a width of the source region, is formed on the source region and the sidewall spacer together.

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Hsinchu, Taiwan

Cheng-Cheng Kuo