Hewlett-packard Company

Other

Agilent Technologies, Inc.

Cheng-Cheng Chang

Jacques Leibovitz

Gary D Sasser

Kim Hong Chen

Andrew Arthur Hunter

Kenneth D Scholz

Voddarahalli K Nagesh

Michael G Kelly

Maria L Cobarruviaz

Lawrence R Hanlon

Susan J Swindlehurst

James-Yu Chang

Park-Kee Yu

Ya Yun Zhu

Bahram Afshari

An optical device packaging technique involves an optical sensor that is formed on a first substrate and flip chip bonded to a second substrate. The second substrate includes a through hole or a transparent section that is aligned with the optical sensor in order to allow light to contact the optical sensor. An embodiment of an optical device structure includes an optical sensor, a first substrate, a second substrate, and a circuit board. The optical sensor is formed on or within the first substrate and the individual sensors or pixels of the optical sensor are electrically connected to contact pads that are exposed on the first substrate. The first substrate is flip chip bonded to the second substrate. The second substrate is flip chip bonded to a circuit board. Another embodiment of an optical device structure includes an optical sensor, a first substrate, and a circuit board as the second substrate. In the embodiment, contact pads of the first substrate are flip chip bonded to contact pads of the circuit board with conductive balls. The connection between the first substrate and the circuit board provides the electrical connection between the optical sensor and the circuit board.

Integrated circuit packaging for optical sensor devices

An integrated circuit redistribution structure. The integrated circuit redistribution structure includes a plurality of conductive pads located on an active side of an integrated circuit. The integrated circuit redistribution structure includes a redistribution layer and an under bump material structure for receiving a solder bump. The redistribution layer can include a first mechanically protective layer which adheres to the active side of the integrated circuit. The redistribution layer includes a plurality of conductive lines in which at least one of the conductive lines is connected to at least one conductive pad. Each conductive line includes an adhesion and diffusion barrier layer, an electrical conductor layer, and a first metallic protective layer. The under bump material structure is formed over at least one conductive line. The under bump material structure includes a solder wettable metal layer formed over the redistribution layer, and a second metallic protective layer for receiving the solder bump.

Redistribution layer and under bump material structure for converting

A flip-chip IC package (10) provides a thermally-conductive lid (20) attached to a backside of the chip (12) by a die attach layer (18) of a predetermined thickness range. A rim (22), preferably KOVAR iron-nickel alloy, is formed on the lid (20) with a depth (44) less than a sum (42) of a thickness of the chip, the interconnects (16), and a minimum final thickness (40) of the die attach layer (18) by a predetermined margin (46). An initial thickness of thermally-filled epoxy is applied to the backside of the chip and a layer of lid attach epoxy (24) is applied to the rim of the lid in a thickness sufficient to span the predetermined margin. The lid is floated on the die attach layer (18) with the rim of the lid surrounding the chip and floating on the lid attach material. The lid is clamped against the chip with a force sufficient to compress the die attach material to a predetermined thickness in a range less than the initial thickness and not less than the minimum final thickness (40). An oxide layer, such as an iron or iron-alloy oxide layer, is formed on the bottom surface of the rim. A spacer is placed on the backside of the chip within the die attach material (18), to define the minimum final thickness (40) of the die attach layer. A beveled or stepped vent hole is formed in the lid and plugged and sealed.

Reliable low thermal resistance package for high power flip clip ICs

A system of interconnecting electrical components having conflicting bonding requirements for mounting the components to a printed circuit board. The system includes a primary printed circuit board having a pattern of through-holes and having arrangements of connection sites to receive electrical components. For example, the connection sites of the primary printed circuit board may be of the type to receive components associated with the bonding requirements of surface mounting. A secondary printed circuit board has a pattern of through-holes corresponding to the pattern of through-holes of the primary printed circuit board. The circuit boards are wave soldered or surface mounted together by means of the corresponding patterns of through-holes. Attached to the secondary printed circuit board is one or more electrical component having bonding requirements which conflict with those of the primary printed circuit board. Preferably, a tape automated bonding frame is in pressure contact with the through-holes of the secondary printed circuit board for electrical communication between the board via the through-holes.

Secondary board for mounting of components having differing bonding

A method and apparatus for electrically connecting circuitry on a printed circuit board having a plurality of circuit regions, with each circuit region having components operatively associated with input and output signal lines that are electrically isolated from the signal lines of adjacent circuit regions. The input and output signal lines of a particular circuit region are arranged in a closely spaced pattern aligned with a corresponding pattern of traces on an adjacent circuit region. A plurality of connector members are selectively attached to the printed circuit board to provide signal communication among the regions. Each connector member has closely spaced conductive bars which are exposed to contact the signal lines. The conductive bars have a length and a pitch such that the bars place parallel trace patterns in electrical communication when pressed in place. The connector members are multi-layered members having the conductive bars attached to a dielectric substrate and having an elastomeric material captured between a dielectric substrate and a metallic cap.

Fault-isolating apparatus and method for connecting circuitry

A semiconductor integrated device support structure having a transmission line interconnect structure in a metal block on which the devices are mounted. The metal block is formed photolithographically from layers which define X,Y sections of the block. A plurality of stacked layers contains the complete wireline interconnect network. Each wire is a true coaxial transmission line having an inner conductor, a surrounding dielectric material and an outer conductor. By appropriate choice of radii of the inner conductor and the surrounding dielectric material, favorable impedances may be selected.

Interconnect structure for integrated circuits

Growing community of inventors

Palo Alto, CA, United States of America

Cheng-Cheng Chang