Promos Technologies, Inc

Winbond Electronics Corporation

China Institute of Technology

China University of Science and Technology

Cheng-Che Lee

Yung-Hsien Wu

Kun-Yi Lee

Wei-Ching Chuang

Wei-Yu Lee

Tsung-De Lin

Chung-Chih Liu

Kuen-Cherng Lin

Chung-Pei Chao

Tao-Yi Chang

Provided is a method for manufacturing a semiconductor device, including: forming a conductive layer on the first dielectric layer; forming a recess in the conductive layer; performing a first etching process to round a top corner of the recess; performing a second etching process to remove the conductive layer exposed from a bottom surface of the recess and thereby forming an opening having a rounding top corner in the conductive layer; and forming a second dielectric layer in the opening.

Method of fabricating semiconductor device

The present invention discloses a method for fabricating an optical filter based on polymer asymmetric bragg couplers using holographic interference techniques, soft lithography, and micro molding, which comprises following steps: prepare a UV polymer with gratings; coating photo-resister film on the UV polymer, and exposed by UV light to obtain a photo-resister mold with two grooves each having gratings; coating diluted PDMS film on the photo-resister mold, and baking the PDMS film to obtain a PDMS mold having two waveguides with gratings; placing glass substrate over the PDMS mold to form a first tunnel; injecting a precure UV polymer into the first tunnel to from a cladding layer with two grooves having gratings pattern at its bottom; placing glass slide over the cladding layer and injecting a mixed UV polymer into the grooves to form waveguide cores; placing a second glass substrate over the cladding layer, and injecting UV polymer to form an upper cladding layer laminated with the cladding layer to obtain the optical filter based on polymer asymmetric bragg couplers.

Optical filters based on polymer asymmetric bragg couplers and its method of fabrication

The present invention discloses a method for fabricating polymer wavelength filter with high-resolution periodical structure, which comprises: a positive photo-resister film is coated or a substrate, holographically exposed with grating pattern, and coated with a negative photo-resister film, then exposed by UV light and developed to obtain a waveguide mold having negative waveguide; a PDMS film coated on the waveguide mold, baked and peeled off to obtain a PDMS mold; a first tunnel formed over the PDMS mold, injected with a first UV polymer, then cured and separated the first UV polymer having groove to be the cladding layer of the polymer wavelength filter; a second UV polymer injected into the groove of the cladding layer, and cured to form the core of the waveguide in the groove of the cladding layer to finally be the polymer wavelength filter.

Polymer wavelength filters with high-resolution periodical structures and its fabrication using replication process

A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is formed in the first dielectric layer. Thereafter, a barrier layer is formed on the first dielectric layer. Afterwards, a BLC is formed in the first opening, and a BL is formed on the first dielectric layer. A liner layer is then formed on a sidewall of the BL. Next, a second dielectric layer having a dry etching rate substantially equal to that of the liner layer and having a wet etching rate larger than that of the liner layer is formed on the substrate. Finally, an SNC is formed in the first and the second dielectric layers.

Method of manufacturing dynamic random access memory

A method of fabricating a capacitor over bit line (COB) is provided. First, a substrate is provided and a plurality of word lines is formed on the substrate. Next, a plurality of landing plug contacts (LPCs) are formed between the word lines and a plurality of first contacts is then formed on the LPCs. Thereafter, a plurality of second contacts is formed on a first portions of the first contacts and a plurality of bit lines connecting a second portions of the first contacts is formed, simultaneously. An inter-layer dielectric (ILD) layer is formed on the substrate to cover the second contacts and the bit lines. Subsequently, a plurality of capacitors is formed in the ILD layer. Thus, the fabrication of the capacitor is simplified.

Method of fabricating capacitor over bit line and bottom electrode thereof

A capacitor dielectric structure of a deep trench capacitor for a DRAM cell is disclosed. A semiconductor silicon substrate is provided with a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N2O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.

Capacitor dielectric structure of a DRAM cell and method for forming thereof

A capacitor dielectric structure of a deep trench capacitor for a DRAM cell. A semiconductor silicon substrate is provided wit a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.

A method of forming capacitor dielectric structure. The method includes steps of providing a semiconductor substrate having at least a predetermined capacitor structure, using silicon nitride deposition to form a SiN layer on the predetermined capacitor structure, using a reoxidation process to grow an oxide layer on the SiN layer, and using a nitridation process with N O as a reactive gas to form a nitridation layer on the oxide layer.

Method of forming a capacitor dielectric structure

A method for forming a layer of silicon nitride that includes providing at least one silicon wafer in a first chamber with ammonia gas, wherein the first chamber is substantially enclosed, and the at least one silicon wafer reacts with the ammonia gas to form a first layer of silicon nitride on the at least one silicon wafer, providing a second chamber with the ammonia gas, moving the at least one silicon wafer into the second chamber, and forming a second layer of silicon nitride on the silicon wafer.

Method for preventing native oxide growth during nitridation

A method for forming a metal interconnect having a plurality of metal lines and an interlayer dielectric is disclosed. The metal interconnect has a decreased capacitance between the metal lines of the metal interconnect. First, a metal interconnect is formed onto a substrate. A first HDPCVD oxide layer is formed over the metal interconnect. A second HDPCVD oxide layer is formed over the first HDPCVD oxide layer, the second HDPCVD oxide layer being formed such that air gaps are formed between the metal lines of the metal interconnect. Furthermore, a third HDPCVD oxide layer may be formed over the second HDPCVD oxide layer, the third HDPCVD oxide formed using a sputter to deposition ratio higher than that used to form the second HDPCVD oxide layer.

Growing community of inventors

Taichung, Taiwan

Cheng-Che Lee