Globalfoundries Singapore Pte. Ltd.

Globalfoundries Inc.

Agency for Science, Technology and Research

Chenchen Jacob Wang

Dimitri Houssameddine

Vinayak Bharat Naik

Taiebeh Tahmasebi

Eng Huat Toh

Kiok Boone Elgin Quek

Michael Nicolas Albert Tran

Kangho Lee

Bin Liu

Chim Seng Seet

Soh Yun Siah

Kazutaka Yamane

Li Wang

Guchang Han

Seungmo Noh

Jinjun Qiu

Wee Kay Yeo

Teck Leong Wee

Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfO. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Storage layer for magnetic memory with high thermal stability

Magnetic field assisted magnetoresistive random access memory (MRAM) structures, integrated circuits including MRAM structures, and methods for fabricating integrated circuits including MRAM structures are provided. An exemplary integrated circuit includes a magnetoresistive random access memory (MRAM) structure and a magnetic field assist structure to generate a selected net magnetic field on the MRAM structure.

Magnetic field assisted MRAM structures, integrated circuits, and methods for fabricating the same

Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode and a base layer over the bottom electrode. The base layer includes a seed layer and a roughness suppression layer. The spin transfer torque magnetic random access memory structure further includes a hard layer over the base layer. Also, the spin transfer torque magnetic random access memory structure includes a magnetic tunnel junction (MTJ) element with a perpendicular orientation over the hard layer and a top electrode over the MTJ element.

Magnetic random access memory structures, integrated circuits, and methods for fabricating the same

Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode, a seed layer over the bottom electrode, a hard layer over the seed layer, a magnetically continuous transition layer over the hard layer, a reference layer over the magnetically continuous transition layer, a tunnel barrier layer over the reference layer, a storage layer formed over the tunnel barrier layer, and a top electrode. The reference layer, the tunnel barrier layer, and the storage layer form a magnetic tunnel junction (MTJ) element with a perpendicular orientation.

One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.

Shielded MRAM cell

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a magnetic tunnel junction. The magnetic tunnel junction includes a fixed layer structure, a free layer structure, and a barrier layer disposed between the fixed layer structure and the free layer structure. The fixed layer structure includes a first magnetic layer and a second magnetic layer that is disposed between the first magnetic layer and the barrier layer. The first magnetic layer is configured to produce a first magnetic moment that substantially correlates to a second magnetic moment of the second magnetic layer as a function of temperature.

Integrated circuits with magnetic tunnel junctions and methods for fabricating the same

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a first and second dummy memory cell positioned within a dummy memory bank area. A first dummy top electrode overlies the first and second dummy memory cells, and is in electrical communication with the first and second dummy memory cells. A test circuit is in electrical communication with the first dummy top electrode.

Integrated circuits with memory cell test circuits and methods for producing the same

One illustrative method disclosed herein includes forming an MRAM memory array and a plurality of peripheral circuits for an integrated circuit product above a semiconductor substrate, forming a patterned layer of a metal-containing shielding material above the substrate, the patterned layer of metal-containing shielding material covering the MRAM memory array while leaving an area above the plurality of peripheral circuits exposed, and, with the patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on the integrated circuit product.

Methods of shielding an embedded MRAM array on an integrated circuit product comprising CMOS based transistors

Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions, and a second selector having a second gate coupled to a second WL and first and second S/D regions. The second S/D regions of the first and the second selectors are a common S/D region. The first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL). The memory cell includes a storage element which includes a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and a voltage control switch which includes a metal-insulator-transition (MIT) material coupled with the first selector.

MRAM with metal-insulator-transition material

Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes forming a storage unit of a magnetic memory cell. A bottom electrode and a fixed layer are formed. The fixed layer includes a composite spacer layer disposed on the bottom electrode. The composite spacer layer includes a base layer and an amorphous buffer layer disposed over the base layer. A reference layer is disposed on the composite spacer layer. The amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation. At least one tunneling barrier layer is formed over the fixed layer. A storage layer is formed over the tunneling barrier layer and a top electrode is formed over the storage layer.

High thermal budget magnetic memory

A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer. The upper ILD layer includes a plurality of ILD levels. A plurality of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. The plurality of MTJ stacks include a first MTJ stack having a first free layer, a first tunneling barrier layer and a first fixed layer. The first free layer is perpendicular to the first tunneling layer and fixed layer in the plane of the substrate surface. The plurality of MTJ stacks also include a second MTJ stack having a second free layer, a second tunneling barrier layer and a second fixed layer.

Integration of spintronic devices with memory device

Memory cells and methods for forming a memory cell are presented. The memory cell includes a storage unit and a selector unit. The storage unit includes a magnetic storage element with first and second storage terminals and a bitline coupled to the second storage terminal. The selector unit includes a first selector and a second selector. The first selector may be a tunneling select transistor or a metal oxide semiconductor select transistor. The second tunneling select transistor is configured to have a second unidirectional current flow between its source and drain terminals. The second selector serves at least as a read selector for read operations of the memory cell and a read current is in the direction of the second unidirectional current flow between the source drain terminals of the second selector.

Magnetic memory cells with fast read/write speed

An ultrahigh differential current perpendicular to the plane dual spin valve read head with high pinning stability. The high pinning stability may be achieved using the same anti-ferromagnetic materials for two spin valves by introducing a double synthetic anti-ferromagnetic structure in one of the two spin valves.

Growing community of inventors

Singapore, Singapore

Chenchen Jacob Wang