Sandisk Technologies Inc.

Sandisk 3D LLC

Chenche Huang

Chun-Ming Wang

Masaaki Higashitani

Johann Alsmeier

Tong Zhang

Jixin Yu

Yuki Mizutani

Masayuki Hiroi

Daxin Mao

Zhenyu Lu

Yuji Takahashi

Kota Funayama

Hiroaki Koketsu

Vincent Shih

Makoto Yoshida

Lauren Matsumoto

A device structure includes an array of semiconductor devices located in an array region over a substrate, metal lines laterally extending from the device region to a peripheral interconnection region, and interconnect via structures located in the peripheral interconnection region, and contacting a portion of a respective one of the plurality of metal lines. The metal lines include a first metal line and a second metal line each having a serpentine region which contacts a respective interconnect via structure.

Interconnects containing serpentine line structures for three-dimensional memory devices and methods of making the same

A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.

Self-aligned isolation dielectric structures for a three-dimensional memory device

A structure is formed on a substrate, which includes a stack of alternating layers comprising insulating layers and electrically conductive layers and a plurality of memory stack structures extending through the stack. At least one bridge line structure is formed on top surfaces of a respective subset of the plurality of memory stack structures to provide local lateral electrical connection. At least one dielectric material layer is formed over the at least one bridge line structure and the plurality of memory stack structures. A plurality contact via structures is formed through the dielectric material layer. The plurality of contact via structures includes at least one first contact via structure contacting a top surface of a respective bridge line structure, and second contact via structures contacting a top surface of a respective memory stack structure.

Bridge line structure for bit line connection in a three-dimensional semiconductor device

A photolithography mask including a plurality of mask features. Adjacent mask features are separated by a gap and are offset from each other such that individual mask features have one-side dense portions and two-side dense portions. Also a photolithography method that includes a step of providing a substantially opaque mask having N stepped rows of offset, substantially transparent, rectangular mask features, where N is an integer and N&#x2267;2. The method also includes illuminating a photoresist layer located over an underlying material with dipole illumination through the substantially transparent, rectangular mask features in the substantially opaque mask to form 2N rows of exposed regions in the photoresist layer. The exposed regions have a substantially elliptical or substantially circular shape when viewed from above the photoresist layer.

Method and mask for enhancing the resolution of patterning 2-row holes

One embodiment of the invention provides a method of forming a plurality of contact holes, including forming a first feature and a second feature over an underlying material, forming sidewall spacers on the first and second features, removing the first and second features without removing the sidewall spacers, forming a cover mask at least partially exposing the sidewall spacers, and etching the underlying material using the cover mask and the sidewall spacers as a mask to form the plurality of contact holes.

Method of forming contact hole arrays using a hybrid spacer technique

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Campbell, CA, United States of America

Chenche Huang