Yangtze Memory Technologies Co., Ltd.

Huazhong University of Science and Technology

Chen Zuo

Zhu Yang

Xiangning Wang

Jingjing Geng

Bin Yuan

Zhen Guo

Jun Yang

Zongke Xu

Qiangwei Zhang

Jiang Huang

Tiaoqin Yu

Lige Zhang

Yongqian Xiong

Xinxin Liu

Mingwu Fan

Jiajia Wu

Gerald F Wu

Lei Cao

Liming Cheng

Kaifeng Liu

Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.

Semiconductor device fabrication

The present disclosure provides a method for forming a three-dimensional (3D) memory. In an example, the method includes forming a stack structure having interleaved a plurality of stack first layers and a plurality of stack second layers, forming a stair in the stack structure, the stair having one of the stack first layers on a top surface, and forming a layer of sacrificial material having a first portion over a side surface of the stair and a second portion over the top surface of the stair. The method also includes partially removing the first portion of the layer of sacrificial material using an anisotropic etching process and removing a remaining portion of the first portion of the layer of sacrificial material using an isotropic etching process.

Methods for forming stairs in three-dimensional memory devices

Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.

Vertical memory devices

Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device includes the following operations. A dielectric stack is formed to have interleaved sacrificial layers and dielectric layers. A stair is formed in the dielectric stack. The stair includes one or more sacrificial layers of the sacrificial layers and one or more dielectric layers of the dielectric layers. The stair exposes one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface. An insulating portion is formed to cover the side surface of the stair to cover the one or more sacrificial layers. A sacrificial portion is formed to cover the top surface of the stair. The sacrificial portion is in contact with the one of sacrificial layers. The one or more sacrificial layers and the sacrificial portion are replaced with one or more conductor layers.

Method and structure for forming stairs in three-dimensional memory devices

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.

Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same

Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.

A system of electron irradiation includes an electron accelerator and an electron beam focusing device. The electron accelerator emits and accelerates a beam of electrons. The electron beam focusing device is located at a rear end of the electron irradiation and includes a beam restraining rail and 2n+1 sets of magnetic poles. The beam restraining rail forms a beam restraining channel through which the beam of electrons are to pass. The 2n+1 sets of magnetic poles are installed on the beam restraining rail and distributed at different locations of the beam restraining channel. An nth set of magnetic poles thereof are arranged for performing, on the beam of electrons, focusing in a first direction. An (n+1)th set of magnetic poles thereof are arranged for performing, on the beam of electrons, focusing in a second direction. The second direction is perpendicular to the first direction. The n is a positive integer.

System of electron irradiation

Provided is a device for optimizing a diffusion section of an electron beam, comprising two groups of permanent magnets, a magnetic field formed by the four magnetic poles extending the electron beam in a longitudinal direction, and compressing the electron beam in a transverse direction, so that the electron beam becomes an approximate ellipse; another magnetic field formed by the eight magnetic poles optimizing an edge of a dispersed electron-beam bunch into an approximate rectangle; by controlling the four longitudinal connection mechanisms so that the upper magnetic yoke and the lower magnetic yoke of the first group of permanent magnets move synchronously towards the center thereof thereby longitudinally compressing the electron beam in the shape of an approximate ellipse, and the upper magnetic yoke and the lower magnetic yoke of the second group of permanent magnets move synchronously towards the center thereof thereby longitudinally compressing the electron beam in the shape of an approximate rectangle, and the process of longitudinal compression is repeated until a longitudinal size of the electron-beam bunch is reduced to 80 mm. The invention is capable of reasonably compressing a longitudinal size of an electron-beam bunch after diffusion to approximately 80 mm, which ensures optimum irradiation uniformity and efficiency, and enables the longitudinal size to be within the range of a conventional titanium window.

Growing community of inventors

Wuhan, China

Chen Zuo