International Business Machines Corporation

Emc IP Holding Company LLC

National Instruments Corporation

Apple Inc.

Shanghai Jiaotong University

Ge Precision Healthcare LLC

Baoshan Iron & Steel Co., Ltd.

State Grid Corporation of China

Medshine Discovery Inc.

Wind Power Technology Center of Gansu Electric Power Company

Gansu Electric Power Company of State Grid

Compagnie Plastic Omnium

Elpis Technologies Inc.

Yanfeng Plastic Omnium Automotive Exterior Systems Co., Ltd.

Fujian Cosunter Pharmaceutical Co., Ltd.

Chen Zhang

Kangguo Cheng

Xin Miao

Wenyu Xu

Tenko Yamashita

Ruilong Xie

Peng Xu

Heng Wu

Chun Wing Yeung

Junli Wang

Alexander Reznicek

Juntao Li

Julien Frougier

Joshua M Rubin

Zhenxing Bi

Brent A Anderson

Lan Yu

Zuoguang Liu

Philip Joseph Oldiges

Dechao Guo

Chun-Chen Yeh

Oleg Gluschenkov

Cheng Chi

Dazhi Dong

Binhua Lu

Sung Dae Suk

Terry Hook

Bruce Bennett Doris

Nicolas J Loubet

Shogo Mochizuki

Terence B Hook

Zheng Xu

Shuhui Chen

Jian Li

Indira P Seshadri

Dongbing Shao

Qiliang Xu

Ardasheir Rahman

Zhengyu Li

Xing Chen

Yijun Shi

Devendra K Sadana

Lawrence Alfred Clevenger

Takashi Ando

Ruqiang Bao

Jingyun Zhang

Ekmini Anuja De Silva

Chi-Chun Liu

Koji Watanabe

Huiming Bu

Christopher Joseph Waskiewicz

Shahab Siddiqui

Chih-Hsiung Liu

Elvis Mwenda Kibiti

Somnath Ghosh

Liang Lu

Ming Gao

Wenyuan Qian

Xiaogang Wang

Changqing Wei

Teresa Jacqueline Wu

Nancy Ellen Kho

Xu Cai

Ningbo Wang

Kun Ding

Jin Li

Shiyuan Zhou

Yonggang Liao

Jianguo Shen

Chih-Chao Yang

Carl John Radens

Chanro Park

Hemanth Jagannathan

Benjamin David Briggs

Fee Li Lie

Yan Chen

Yu Chen Zhou

Wei Ey Li

Dexin Kong

Haiying He

Huimei Zhou

Jie Hui Xu

Jing Wang

Li Yang

Pietro Montanini

Lu Wang

Yi Song

Chia Chi Wu

James Odis Pendergraft

Zhigan Jiang

Jie Yang

Jun Lin

Zhen Gong

ChoongHyun Lee

Eric Miller

Norman Speciner

Zhoushe Zhao

Yaxun Yang

Daniel Stanton Keefe

Yao Xiao

A top via interconnect with enlarged via top and a fabrication method therefor. One embodiment may comprise a semiconductor interconnect structure, comprising a first dielectric layer having a top surface, a bottom metal line formed in the dielectric layer, a second dielectric layer deposited above the top surface of the first dielectric layer, a via etched through the second dielectric layer above the bottom metal line, wherein the via exposes at least a portion of the top surface of the first dielectric layer, and a metal stud in the via that extends over the exposed at least a portion of the first dielectric layer. The metal stud in the via may further comprise a shoulder surface and a convex top surface.

TopVia interconnect with enlarged via top

Semiconductor devices, and methods of forming the same, include forming a stack of channel layers, including an upper device region and a lower device region. The upper device region is separated from the lower device region by a dielectric spacer layer. A first work function metal layer is formed on the channel layers in the lower device region. A height of the first work function metal layer does not rise above the dielectric spacer layer. A second work function metal layer is formed on the channel layers in the upper device region.

Work function metal patterning for nanosheet CFETs

A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width Wand the first nanosheet is tapered in the X-direction to have a length L. A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width Wand the first nanosheet is tapered in the X-direction to have a length L. Wherein the widths Wand Ware different from each other and the lengths Land Lare different from each other and wherein the substrate includes a tapered surface in the Y-direction.

Gate-all-around nanosheet-FET with variable channel geometries for performance optimization

A plurality of transistor components, a system, and a method of forming a vertically stacked transistor structure within a wafer. The plurality of transistor components may include a first bottom transistor, where the first bottom transistor includes a channel, a gate, a source, and a drain. The plurality of transistor components may also include a first contact on top of the first bottom transistor, where the first contact is proximately connected to the first bottom transistor. The plurality of transistor components may also include a first set of stacked transistors, where the first set of stacked transistors includes a second top transistor on top of a second bottom transistor.

Dummy fin contact in vertically stacked transistors

A semiconductor device includes a FinFET fin. The same FinFET fin is associated with a bottom FinFET and a top FinFET. The FinFET fin includes a lower channel portion, associated with the bottom FinFET, a top channel portion, associated with the top FinFET, and a channel isolator between the bottom channel portion and the top channel portion. A lower gate includes a vertical portion that is upon a sidewall of the bottom channel portion. An isolation layer may be formed upon the lower gate if it is desired for the top FinFET fin and the bottom FinFET fin to not share a gate. An upper gate is upon the top channel portion and is further upon the isolation layer, if present, or is upon the lower gate.

Upper and lower gate configurations of monolithic stacked FinFET transistors

Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.

Hybrid gate cut for stacked transistors

A set of stacked transistors, system, and method to connect the gates of stacked field-effect transistors through sidewall straps. The set of stacked transistors may include a first transistor including a first gate. The set of stacked transistors may also include a second transistor including a second gate, where the second transistor is above the first transistor. The set of stacked transistors may also include a dielectric preventing direct contact between the first gate and the second gate. The set of stacked transistors may also include a first sidewall strap proximately connected to the first gate and the second gate, where the first sidewall strap connects the first transistor and the second transistor.

Stacked FET sidewall strap connections between gates

A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.

Buried power rail formation for vertical field effect transistors

Provided in the present application are a method and a device for extracting a blood vessel wall, a medical imaging system, and a non-transitory computer-readable storage medium. The method for extracting a blood vessel wall comprises acquiring a medical image, determining at least one first-order feature in the medical image, and extracting, on the basis of the at least one first-order feature, a blood vessel wall image from the medical image.

Method and device for extracting blood vessel wall

Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.

Stacked nanosheet transistor with defect free channel

A uniform moon-shaped bottom spacer for a VTFET device is provided utilizing a replacement bottom spacer that is epitaxially grown above a bottom source/drain region. After filling a trench that is formed into a substrate with a dielectric fill material that also covers the replacement bottom spacer, the replacement bottom spacer is accessed, removed and then replaced with a moon-shaped bottom spacer.

Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices

A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

Three-dimensional, monolithically stacked field effect transistors formed on the front and backside of a wafer

A stacked field-effect transistors (FETs) layout and a method for fabrication are provided. The stacked FETs include a buried interconnect within the stacked devices which provides power to buried components without requiring a wired connection from a top of the stacked FET to the buried components. The buried interconnect allows for efficient scaling of the stacked devices without extraneous wiring from a top of the device to each epitaxial region/device within the overall device.

Stacked device with buried interconnect

A complementary metal-oxide semiconductor device formed by fabricating CMOS nanosheet stacks, forming a dielectric pillar dividing the CMOS nanosheet stacks, forming CMOS FET pairs on either side of the dielectric pillar, and forming a gate contact for at least one of the FETs.

Complementary field effect transistor devices

A neural network device comprises a first plurality of synapse network capacitors, wherein the synapse network capacitors of the first plurality of synapse network capacitors share a first output terminal. The neural network device further comprises a second plurality of synapse network capacitors, wherein the synapse network capacitors of the second plurality of synapse network capacitors share a second output terminal. Still further, the neural network device comprises a metal shielding disposed between the first output terminal and the second output terminal. The neural network device may be used as part of an artificial intelligence system.

Capacitor-based synapse network structure with metal shielding between outputs

Growing community of inventors

Guilderland, NY, United States of America

Chen Zhang