Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Chen-Yuan Kao

Hung-Wen Su

Mei-Yun Wang

Kuo-Yi Chao

Chao-Hsun Wang

Rueijer Lin

Feng-Yu Chang

Chih-Chien Chi

Yao-Jen Chang

Po-Cheng Shih

Kai-Shiang Kuo

Jun-Yi Ruan

Liang-Yueh Ou Yang

Yu-Feng Yin

Syun-Ming Jang Jang

Ming-Hsing Tsai

Yu-Sheng Wang

Po-Yu Huang

Shih-Che Lin

Wen-Jiun Liu

Tze-Liang Lee

Yi-Wei Chiu

Chung-Chi Ko

Chi-Cheng Hung

Yueh-Ching Pai

Chia-Cheng Chou

Min-Hsiu Tsai

Chih-Yi Chang

Wei-Jung Lin

Minghsing Tsai

Hong-Ming Wu

Chun-Hsien Huang

Chun-Chieh Lin

Huang-Yi Huang

Ken-Yu Chang

Chia-Han Lai

Tse-Wei Wu

Yu-Syuan Cai

Chih-Wei Chang

Fu-Kai Yang

Jyu-Horng Shieh

Yu-Ting Lin

Sheng-Liang Pan

Cheng-Wei Chang

Peng-Fu Hsu

Chun-I Tsai

Min-Hsiu Hung

Yi-Ying Liu

Shu-Huei Suen

Shao-Jyun Wu

Chia-Yang Hung

I-Li Chen

Ting-Yu Chen

Jack Kuo-Ping Kuo

Pang-Sheng Chang

Chia-Sheng Chang

Li-Hsiang Chao

Hsin-Lung Li

Yu-Hsun Su

Mingh-Hsing Tsai

Yu-Lun Wan

Bor-Yueh Liu

Yu-Chan Tsai

A testing circuit is provided. The testing circuit includes a clock cone, a series of shift register chains, and a control circuit. The clock cone is divided into a plurality of fan-out partitions operated in the same clock domain. The shift register chains are configured to shift out one-hot signals on demand and each shift register chain includes multiple registers with the same amount as fan-out partitions. The control circuit receives the one-hot signals from the shift register chains and enables the divided fan-out partitions therefore.

Testing circuit

A capture IR drop analyzer and an analyzing method thereof are provided. The capture IR drop analyzing method includes: receiving circuit layout information and package model information of a circuit; analyzing a plurality of circuit blocks respectively corresponding to a plurality of bump current sources according to the circuit layout information and the package model information; calculating at least one critical circuit block according to each of the bump current sources and a current demand value of each of the corresponding circuit blocks; and analyzing a clock tree architecture of the at least one critical circuit block to obtain design structure adjustment information.

Capture IR drop analyzer and analyzing method thereof

Some implementations described herein provide a gas curtain system. The gas curtain system includes various components to prevent a gas flowing within a chamber of an interface tool from flowing through an opening into a transport carrier adjacent to the interface tool. The gas curtain system may include a gas distribution component along an edge of the opening that generates a flow of another gas across the opening towards an opposite edge of the opening. In this way, the gas from the chamber is prevented from entering the transport carrier. By preventing the gas from the chamber from entering the transport carrier, a relative humidity within an environment of the transport carrier is maintained such that condensation of moisture on one or more semiconductor wafers within the transport carrier is mitigated.

Interface tool and methods of operation

A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.

Forming metal contacts on metal gates

Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Different via configurations for different via interface requirements

A method for forming a FinFET device structure is provided. The method includes forming a gate dielectric layer over a fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer. The method further includes forming a first dielectric layer formed over the gate dielectric layer. In addition, the method includes forming a first conductive layer on the gate dielectric layer. A bottom surface of the first conductive layer is in direct contact a top surface of the gate electrode layer, a sidewall of the first conductive layer is in direct contact the first dielectric layer and spaced apart from the gate dielectric layer.

Method for forming fin field effect transistor (FinFET) device structure with conductive layer between gate and gate contact

A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Multi-layer film device and method

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Chemical direct pattern plating method

A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Methods for forming contact plugs with reduced corrosion

In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Interconnect structures including a fin structure and a metal cap

A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Vertical interconnect features and methods of forming

A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

Common rail contact

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Zhudong, Taiwan

Chen-Yuan Kao