Macronix International Co., Ltd.

Industrial Technology Research Institute

Chen-Yu Cheng

Tzung-Ting Han

Shih Chin Lee

Ching Hung Wang

Je-Ping Hu

Dong-Sing Wuu

Yi-Yung Wu

Yih-Shing Lee

A semiconductor device includes a circuit board, a bottom plate, landing pads, a stack, support pillars, and memory pillars. The circuit board includes circuit structures and wires and has a peripheral area, an array area and a staircase area disposed between the peripheral area and the array area. The bottom plate is disposed on the circuit board, and the bottom plate includes a bottom conductive layer. The landing pads are embedded in at least a top portion of the bottom conductive layer and contact the bottom conductive layer in the staircase area. The stack is disposed on the bottom plate, and includes conductive layers and insulating layers alternately stacked along a first direction. The support pillars pass through the stack along the first direction and extend to the landing pads in the staircase area. The memory pillars pass through the stack along the first direction in the array area.

Semiconductor device and method for manufacturing the same

Provided is a memory device including a substrate, a stack structure, a plurality of pads and an additional dielectric layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The additional dielectric layer is disposed on the stack structure to contact a topmost conductive layer of the conductive layers. A topmost pad of the pads includes a landing portion to contact a plug and an extension portion. The landing portion is laterally adjacent to the additional dielectric layer, and the extension portion extends over a top surface of the additional dielectric layer.

Memory device

A memory device includes a substrate, a stack structure, a first staircase structure, and a first part of a second staircase structure. The substrate includes a plurality of blocks each having a staircase region, a memory array region, and a word line cutting region. The stack structure is located on the substrate in the memory array region, and includes first insulating layers and conductive layers alternately stacked on each other. The first staircase structure is located on the substrate in the staircase region, and includes first insulating layers and conductive layers alternately stacked on each other. The first part of the second staircase structure is located on the substrate in the word line cutting region, and includes first insulating layers and conductive layers alternately stacked on each other, and two first parts of two second staircase structures in two adjacent blocks are separated from each other.

Memory device and method of fabricating the same

Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.

Memory device and method of manufacturing the same

Methods and apparatus for fabricating memory devices are provided. In one aspect, an intermediate stack of dielectric layers are formed on a first stack of dielectric layers in a first tier. The intermediate stack of dielectric layers is then partially or fully etched and have a landing pad layer deposited thereon. In response to planarizing the landing pad layer to expose a top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers are deposited above the planarized landing pad layer. A staircase is formed by etching through the second stack, the intermediate stack, and the first stack of dielectric layers in the staircase region of the memory device. The staircase is located adjacent to one end of the center landing pad, where steps of the staircase are formed within the thickness of the center landing pad.

Semiconductor memory structure and manufacturing method thereof

A manufacturing method of monolithic integrated thermal bubble inkjet print heads and the structure for the same. The method utilizes semiconductor manufacturing technologies to configure various elements in a thermal bubble inkjet print head, such as ink channels, an ink slot, an energy transducer, an orifice plate, on a single substrate. The ink channels are formed on an top surface of the substrate using the anisotropic etching technique. The ink slot is formed on a back surface of the substrate using the anisotropic etching technique. The energy transducer and the orifice plate are formed in order above the ink channels using the coating and etching techniques. This thermal bubble inkjet print head manufacturing method is particularly useful in the all batch process without employing the steps of precision alignment joint for the orifice plate in a conventional inkjet print head. Therefore, the method can greatly increase production efficiency and lower production costs.

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Hsinchu, Taiwan

Chen-Yu Cheng