Taiwan Semiconductor Manufacturing Comp. Ltd.

Lite-on Technology Corporation

Silitek Electronic (guangzhou) Co., Ltd.

Lite-on Electronics (guangzhou) Limited

Chen-Yu Chen

Ming-Feng Shieh

Ching-Yu Chang

Yan-Yu Wang

Chih-Lung Liang

Chih-Ming Lai

Wen-Chun Huang

Nian-Fuh Cheng

Wei-Chao Chiu

Ru-Gun Liu

Hung-Chang Hsieh

Shun-Chung Cheng

Yu-Kang Lu

Ru-Gun Lin

An overlay mark includes a first feature extending in an X-direction, wherein the first feature is a first distance from a substrate. The overlay mark further includes a second feature extending in a Y-direction perpendicular to the X-direction, wherein the second feature is a second distance from the substrate, and the second distance is different from the first distance, wherein at least one of the first feature or the second feature comprises a conductive material. The overlay mark further includes a third feature extending in the X-direction and the Y-direction, wherein the third feature is a third distance from the substrate, and the third distance is different from the first distance and the second distance. The first distance, the second distance and the third distance from the substrate are along a Z-direction perpendicular to both the X-direction and the Y-direction.

Overlay mark and method of making

An overlay mark includes a first feature extending in an X-direction, wherein the first feature is a first distance from a substrate. The overlay mark further includes a second feature extending in a Y-direction perpendicular to the X-direction, wherein the second feature is a second distance from the substrate, and the second distance is different from the first distance. The overlay mark further includes a third feature extending in the X-direction and the Y-direction, wherein the third feature is a third distance from the substrate, and the third distance is different from the first distance and the second distance.

Overlay mark

A method of forming an overlay mark includes disposing a first feature of a plurality of first alignment segments extending along a first direction in a first layer, disposing a second feature of a plurality of second alignment segments extending along a second direction in a second layer over the first layer, and forming a third feature of a plurality of third alignment segments extending along the first direction and a plurality of fourth alignment segments extending along the second direction in a third layer over the second layer. In a plan view, each first alignment segment of the first alignment segments is adjacent to a corresponding third alignment segment of the third alignment segments along the first direction, and each second alignment segment of the second alignment segments is adjacent to a corresponding fourth alignment segment of the fourth alignment segments along the second direction.

An overlay mark includes a first feature of a plurality of first alignment segments extending along a first direction in a first layer, a second feature of a plurality of second alignment segments extending along a second direction in a second layer over the first layer, and a third feature of a plurality of third alignment segments extending along the first direction and a plurality of fourth alignment segments extending along the second direction in a third layer over the second layer. In a plan view, each first alignment segment of the plurality of first alignment segments is adjacent to a corresponding third alignment segment of the plurality of third alignment segments along the first direction, and each second alignment segment of the plurality of second alignment segments is adjacent to a corresponding forth alignment segment of the plurality of fourth alignment segments along the second direction.

An overlay mark comprises a first feature in a first layer. The first feature has a length extending in a first longitudinal direction and a width extending in a second longitudinal direction. The length of the first feature is greater than the width of the first feature. The overlay mark also comprises a second feature in a second layer over the first layer. The second feature has a length extending in the second longitudinal direction and a width extending in the first longitudinal direction. The length of the second feature is greater than the width of the second feature. The overlay mark further comprises a third feature in a third layer over the second layer. The third feature is a box-shaped opening in the third layer.

A method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.

Method of patterning features of a semiconductor device

A semiconductor device includes a substrate and a plurality of fin structures. A first fin structure and a second fin structure are spaced at a distance D. A first dummy fin structure is adjacent to the first fin structure, and a second dummy fin structure is adjacent to the second fin structure. The device further includes an isolation layer over the substrate and the first and second dummy fin structures, and surrounding the first and second fin structures. The fin structures are arranged such that a distance Dbetween the first fin structure and the first dummy fin structure is greater than the distance D

Method of fabricating a FinFET device

The present disclosure provides a method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.

A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. A plurality of mandrel features are formed on a substrate. First spacers are formed along sidewalls of the mandrel feature and second spacers are along sidewalls of the first spacers. Two back-to-back adjacent second spacers separate by a gap in a first region and merge together in a second region of the substrate. A dielectric feature is formed in the gap and a dielectric mesa is formed in a third region of the substrate. A first subset of the first spacer is removed in a fine cut. Fins and trenches are formed by etching the substrate using the first spacer and the dielectric feature as an etch mask.

Method of making a FinFET device

A method includes receiving a substrate having an etch stop layer deposited over the substrate and a dummy mandrel layer deposited over the etch stop layer, forming a plurality of hard mask patterns using a hard mask layer deposited over the dummy mandrel layer, wherein the hard mask patterns includes a first dimension adjusted by a predetermined value, depositing a first spacer layer over the hard mask patterns, wherein a thickness of the first spacer layer is adjusted by the predetermined value, forming a plurality of spacer fins in the dummy mandrel layer, wherein the spacer fins include a second dimension, a first space, and a second space, performing a first fin cut process to remove at least one spacer fin, adjusting the second dimension to a target dimension, performing a second fin cut process, and forming a plurality of fin structures in the substrate by etching the spacer fins.

A device having an overlay mark over a substrate and a method of adjusting multi-layer overlay alignment using the overlay mark for accuracy are disclosed. The overlay mark includes a first feature in a first layer, having a plurality of first alignment segments substantially parallel to each other extending only along an X direction; a second feature in a second layer over the first layer, having a plurality of second alignment segments substantially parallel to each other extending along a Y direction different from the X direction; and a third feature in a third layer over the second layer, having a plurality of third alignment segments substantially parallel to each other extending along the X direction and a plurality of fourth alignment segments substantially parallel to each other extending along the Y direction.

Overlay mark and method of measuring the same

A light emitting diode (LED) includes a substrate, a temperature detecting pattern, and a semiconductor structure. The temperature detecting pattern is formed on the substrate. Then the semiconductor structure is formed on the temperature detecting pattern and the substrate. The semiconductor structure includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer. Per above-mentioned structural design, the temperature detecting pattern directly integrated into the LED can measure the actual temperature of PN junction with high precision.

Light emitting diode with a temperature detecting pattern and manufacturing method thereof

A method of forming a fin structure of a semiconductor device includes providing a substrate, creating a mandrel pattern over the substrate, depositing a first spacer layer over the mandrel pattern, and removing portions of the first spacer layer to form first spacer fins. The method also includes performing a first fin cut process to remove a subset of the first spacer fins, depositing a second spacer layer over the un-removed first spacer fins, and removing portions of the second spacer layer to form second spacer fins. The method further includes forming fin structures, and performing a second fin cut process to remove a subset of the fin structures.

An LED module includes at least two LED package units and at least one connecting unit. Each LED package unit includes at least one first engaging portion, at least one first conductive portion, and at least one LED chip connected electrically to the first engaging portion. The connecting unit includes at least two second engaging portions, and at least one second conductive portion having two opposite end sections extending respectively to the second engaging portions. When the second engaging portions of the connecting unit engaged with the first engaging portions of the LED package units, respectively, the end sections of the second conductive portion contact electrically and respectively the corresponding first conductive portions so as to connect electrically the LED chips of the LED package units.

LED module

A lamp includes a lamp holder module and light-emitting module disposed in the lamp holder module. The lamp holder module includes a body, a pressing mechanism disposed on the body, and an upper cover engaging removably the body. The light-emitting module is placed on the body and is pressed into position through the pressing mechanism. The pressing mechanism is operable to release the light-emitting module, thereby facilitating removal and installation of the light-emitting module. The upper cover serves as a lens of the light-emitting module and covers the light-emitting module.

Growing community of inventors

Taipei, Taiwan

Chen-Yu Chen