Tencent Technology (shenzhen) Company Limited

Zte Corporation

The Chinese University of Hong Kong

Sanechips Technology Co., Ltd.

Chen Yu

Bin Zhou

Lan Liu

Liang Wu

Jie Xiao

Fengbo Wu

Bian Wu

Zehui Kang

A harmonic oscillator realizing harmonic tuning based on harmonic current selection is provided. The harmonic oscillator includes a first MOS transistor M, a second MOS transistor M, a first inductor L, a second inductor L, a third inductor L, a fourth inductor L, a fifth inductor L, a first variable capacitor C, a second capacitor C, a first fixed capacitor C, a second fixed capacitor Cand a switched capacitor array SCA. By suppressing a second harmonic current and promoting a third harmonic current, the invention avoids the design complexity caused by synchronous tuning of two types of harmonic impedances. By suppressing a second harmonic current and promoting a third harmonic current, the design complexity caused by synchronous tuning of two types of harmonic impedances is avoided.

Harmonic oscillator realizing harmonic tuning based on harmonic current selection

A method of facilitating an operating terminal to control media information displayed on target terminals using a computer server is disclosed. Upon receipt of a search request for target terminals within a local area network from an operating terminal, the computer server identifies a list of online terminals as the target terminals and returns the target terminals to the operating terminal. A user of the operating terminal then generates an operation instruction for controlling media information displayed on the target terminals. In response to the operation instruction, the computer server sends the operation instruction to respective applications running on the target terminals. The respective applications are configured to control the media information displayed on the target terminals in accordance with the operation instruction.

Method and system for controlling media information display on multiple terminals

Disclosed is a chip-based data transmission method for a data sending side. The method includes that protocol layer processing is performed on input data, and the data after the protocol layer processing is mapped to each physical channel for transmission; meta-frame layer processing is performed on the data transmitted by each physical channel, and the data after the meta-frame layer processing is sent. Another chip-based data transmission method for a data receiving side is provided which includes that meta-frame layer processing is performed on data received by each physical channel, the data after the meta-frame layer processing is mapped to a protocol layer for transmission, and the protocol layer processing is performed on the data transmitted by the protocol layer, and the data after the protocol layer processing is sent. A chip-based data transmission device and system, and a computer storage medium are also provided.

Chip-based data transmission method, device and system, and computer storage medium

A method and an apparatus for calculating packet arrival time interval are provided by the present invention. In the above-mentioned method, when the current packet arrives, system current time Tis read from a timer, and the arrival time T, recorded in an external RAM, of previous packet of the flow to which the current packet belongs is read (), wherein the timer implements a cycle timing with a period of preset time period T, the preset time period Tis larger than or equal to the time for filling the maximum depth of the token bucket of the flow at the minimum token injection rate; a current flag bit, recorded in an internal RAM, of the flow to which the current packet belongs is read (), wherein the current flag bit is used for indicating the number of cycles of the timer between the system current time Tand the arrival time Tof previous packet; and the arrival time interval of the present packet is calculated according to the system current time T, the arrival time Tof previous packet and the current flag bit (). Application of the present invention can reduce the consumption of the internal RAM and improve the operability for realizing by the hardware chips.

Method and apparatus for calculating packet arrival time interval

Growing community of inventors

Shenzhen, China

Chen Yu