International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Chen-Yong Cher

Pradip Bose

Eren Kursun

Alper Buyuktosunoglu

Yoonho Park

Bryan Savoye Rosenburg

Kyung D Ryu

Carlos Henrique Andrade Costa

Haifeng Qian

Michael K Gschwind

Ravi Nair

Paul William Coteus

Alan G Gara

Prabhakar Nandavar Kudva

Hans Mikael Jacobson

Keith Aelwyn Jenkins

Barry P Linder

Karthik V Swaminathan

Jose R Brunheroto

Ramon Bertran Monfort

Valentina Salapura

Dong Chen

John Edward Sheets, Ii

Michael A Blocksome

Hubertus Franke

Joseph D Ratterman

Philip Heidelberger

Adam James Muff

David Paul Paulsen

Todd Edward Takken

Martin Ohmacht

Bruce Martin Fleischer

Alexandre E Eichenberger

Thomas M Gooding

Robert William Wisniewski

John A Gunnels

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Sameh W Asaad

Matthias Augustin Blumrich

Shawn Anthony Hall

Thomas Winters Fox

John Kevin O'Brien

Barry Marshall Trager

Peng Wu

Shurong Tian

Charles David Wait

Sameer Kumar

James Anthony Marcella

Todd Alan Inglett

George L Chiu

Krishnan Sugavanam

Augusto Javier Vega

Gerard Vincent Kopcsay

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

Rudolf Adriaan Haring

Craig Brian Stunkel

David L Satterfield

Douglas R Miller

Yutaka Sugawara

Amith R Mamidala

Kristan D Davis

Michael B Mundy

Matthew Roger Ellavsky

Brian Andrew Schuelke

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Ruth Janine Poole

Gabor J Dozsa

Brant L Knudson

Peter Boyle

Ralph E Bellofatto

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Hendrik F Hamann

Brian E Smith

Wilfried Haensch

Ashish Jagmohan

Michele M Franceschini

Vijayalakshmi Srinivasan

Srinivasan Ramani

Victor V Zyuban

Alan Weger

Robert Alan Philhower

Gary William Maier

Raymond Cheung Yeung

Raphael Peter Robertazzi

Tejas S Karkhanis

David R Motschman

Zhigang Hu

Wolfram Sauer

Jamin Naghmouchi

Pierce I Chuang

There is provided a method for managing a solid state storage system with hybrid storage technologies. The method includes monitoring one or more storage request streams to identify operating mode characteristics therein from among a set of possible operating mode characteristics. The set of possible operating mode characteristics correspond to a set of available operating modes of the hybrid storage technologies. The method further includes identifying a current operating mode from among the set of available operating modes responsive to the identified operating mode characteristics. The method also includes predicting a likely future operating mode responsive to variations in workload requirements to generate at least one future operating mode prediction. The method additionally includes controlling at least one of data placement, wear leveling, and garbage collection, responsive to the at least one future operating mode prediction.

Managing high performance storage systems with hybrid storage technologies

A method for managing a network queue memory includes receiving sensor information about the network queue memory, predicting a memory failure in the network queue memory based on the sensor information, and outputting a notification through a plurality of nodes forming a network and using the network queue memory, the notification configuring communications between the nodes.

Network resiliency through memory health monitoring and proactive management

An integrated circuit (IC) includes: a plurality of hardware performance counters; a thermal sensor; and a micro-controller. The micro-controller generates a plurality of thermal predictors based on values of the counters and temperatures sensed by the thermal sensor. The thermal predictors include first and second rising thermal delta predictors to predict rising temperature deltas and first and second falling thermal delta predictors to predict falling temperature deltas. The micro-controller predicts a future temperature of the IC based on an idle temperature of the IC and a selected one of the temperature deltas.

Chip transient temperature predictor

A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (V), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.

Reliability-aware runtime optimal processor configuration

A method and circuit of monitoring an effective age of a target circuit are provided. A standby mode is activated in the target circuit. A standby current of a first number of circuit blocks of the target circuit is measured. The measured standby current of the first number of circuit blocks is compared to a first baseline standby current of the first number of circuit blocks. Upon determining that the measured standby current of the first number of circuit blocks is below a first predetermined factor of a baseline standby current of the first number of circuit blocks, the first number of circuit blocks is identified to have a bias temperature instability (BTI) degradation concern.

Dynamic predictor of semiconductor lifetime limits

An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.

Optimization of application workflow in mobile embedded devices

According to an aspect, a method for triggering creation of a checkpoint in a computer system includes executing a task in a processing node of the computer system. A monitoring block size is determined for the checkpoint. A checkpoint interval is determined based on the monitoring block size, a checkpoint bandwidth, and a failure rate of the computer system. Based on determining that the checkpoint interval has elapsed, the checkpoint including state data of the task is created to enable restarting execution of the task upon a restart operation. The state data of the checkpoint is restored from a memory responsive to detecting an error condition at the processing node. Execution of the task is restarted in the processing node based on the state data restored from the memory.

Checkpoint triggering in a computer system

A method is disclosed, as well as an associated apparatus and computer program product, for checkpointing using a plurality of communicatively coupled compute nodes. The method comprises acquiring health information for a first node of the plurality of compute nodes, and determining a first failure probability for the first node using the health information. The first failure probability corresponds to a predetermined time interval. The method further comprises selecting a second node of the plurality of compute nodes as a partner node for the first node. The second node has a second failure probability for the time interval. A composite failure probability of the first node and the second node is less than the first failure probability. The method further comprises copying checkpoint information from the first node to the partner node.

Checkpointing using compute node health information

Over at least part of a lifetime of a product circuit, quiescent current to a product circuit is periodically measured. Over the part of the lifetime of the product circuit, voltage to the product circuit is periodically adjusted based on the monitored quiescent current. Methods, apparatus, and computer program product are disclosed. A calibration procedure may also be performed as part of manufacturing the product circuit, in order to provide values for the quiescent current and corresponding voltage to which the voltage should be adjusted.

Autonomic supply voltage compensation for degradation of circuits over circuit lifetime

A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ECC) configuration corresponding to the portion of the memory; determining whether the active ECC configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ECC configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot be tolerated by the application, determining whether a stronger ECC level is available and, if a stronger ECC level is available, increasing a strength of the active ECC configuration; and when data corruption can be tolerated, performing page reassignment and aggregation of non-critical data.

Method and apparatus for selective and power-aware memory error protection and memory management

According to an aspect, a method for triggering creation of a checkpoint in a computer system includes executing a task in a processing node and determining whether it is time to read a monitor associated with a metric of the task. The monitor is read to determine a value of the metric based on determining that it is time to read the monitor. A threshold for triggering creation of the checkpoint is determined based on the metric. A monitoring block size is determined for the checkpoint. A checkpoint interval is determined based on the monitoring block size, a checkpoint bandwidth, and a failure rate of the computer system. Based on determining that the value of the metric has crossed the threshold and the checkpoint interval has elapsed, the checkpoint including state data of the task is created to enable restarting execution of the task upon a restart operation.

A method for selective duplication of subtasks in a high-performance computing system includes: monitoring a health status of one or more nodes in a high-performance computing system, where one or more subtasks of a parallel task execute on the one or more nodes; identifying one or more nodes as having a likelihood of failure which exceeds a first prescribed threshold; selectively duplicating the one or more subtasks that execute on the one or more nodes having a likelihood of failure which exceeds the first prescribed threshold; and notifying a messaging library that one or more subtasks were duplicated.

Methods, apparatus and system for selective duplication of subtasks

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

Method of measuring semiconductor device leakage which includes: providing a semiconductor device powered by a supply voltage and having a circuit block of transistors; providing on the semiconductor device a test circuit providing an input to a counter and a fixed-frequency measurement clock to provide a clock signal to the counter; disconnecting a system clock from the circuit block; receiving by the test circuit the supply voltage as an input; initializing the counter; starting the counter when the supply voltage is at or below a first voltage V; monitoring a decrease of the supply voltage with time; stopping the counter when the supply voltage is at or below a second voltage Vsuch that Vis greater than V; and reading the counter to provide the semiconductor device leakage metric. Also disclosed is an apparatus and a computer program product.

On-chip leakage measurement

Growing community of inventors

Port Chester, NY, United States of America

Chen-Yong Cher