Au Optronics Corporation

Chen-Yi Wu

Bo-Ru Jian

Chun-Yao Huang

Ta-Wen Liao

Kuei-Sheng Tseng

Hsiang-Pin Fan

Wen-Pin Chen

Yih-Chyun Kao

Tai-Tso Lin

Mei-Hui Lee

Shih-Chyn Lin

Kuo-Hsuan Huang

Shih-Wei Lin

Wei-Liang Chan

Chi-Hsiung Chang

A display device includes a substrate, gate lines, a driving circuit, and auxiliary gate lines. The substrate has a display area. The gate lines are disposed on the display area, and are in parallel with a first edge of the display area. The gate lines include a first gate line which is farthest from the first edge. The driving circuit is disposed adjacent to the first edge. The auxiliary gate lines substantially perpendicular to the gate lines are connected to the gate lines, and are in parallel with a second edge of the display area. The auxiliary gate lines include a first auxiliary gate line and at least one auxiliary gate line. The first auxiliary gate line is configured to connect the first gate line to the driving circuit. The at least one auxiliary gate line is disposed between the second edge and the first auxiliary gate line.

Display device

A display panel includes a first substrate, a second substrate, a display medium layer, pixel units, and a light-shielding conductive pattern layer. The first substrate has a first inner surface and a first outer surface, and the first outer surface serves as a display surface of the display panel. The second substrate is disposed opposite to the first substrate and has a second inner surface and a second outer surface. The display medium layer is disposed between the first inner surface and the second inner surface. The pixel units are disposed between the display medium layer and the first inner surface, and at least one of the pixel units includes an active element. The light-shielding conductive pattern layer is disposed between the display medium layer and the second inner surface, at least partially overlaps the active element in a vertical projection direction, and includes a first patterned light-shielding conductive layer and a first patterned low-reflection layer. The first patterned light-shielding conductive layer is disposed between the first patterned low-reflection layer and the second substrate.

Display panel and display device

A liquid crystal pixel circuit and a driving method thereof are provided. The liquid crystal pixel circuit has a main pixel, a sub pixel and a charge sharing switch. The charge sharing switch is electrically coupled between the main pixel and the sub pixel. The main pixel, the sub pixel and the charge sharing switch are controlled by the same gate line. The provided driving method is used for driving the liquid-crystal pixel circuit mentioned above.

Liquid crystal pixel circuit and driving method thereof

A shift register for providing a plurality of gate signals includes an Nth stage shift register unit and an (N+1)th stage shift register unit. The Nth stage shift register unit includes a first pull up unit, a first driving unit, a first control unit and a first auxiliary pull down unit. The (N+1)th stage shift register unit includes a second pull up unit, a second driving unit, a first pull down unit and a second auxiliary pull down unit. The first and second pull up units are both coupled to the first and second driving units for controlling the first and second driving units to generate gate signals. The first and second auxiliary pull down units are both coupled to the first control unit for pulling down the gate signals.

Shift register

A thin film transistor (TFT) and a pixel structure having the TFT are provided. The TFT is configured on a substrate. Besides, the TFT includes a gate, a gate insulation layer, a source, a channel layer, and a drain. The gate insulation layer covers the gate and the substrate. The source is configured on a portion of the gate insulation layer. The channel layer is configured on the gate insulation layer and covers a portion of the source located above the gate. The drain is configured on and electrically connected to the channel layer.

Thin film transistor and pixel structure having the thin film transistor

A shift register includes a control circuit, a pull-up circuit and a pull-down circuit. The control circuit generates a control signal according to a start pulse signal during being enabled. The pull-up circuit produces a gate pulse signal according to a clock signal during being enabled by the control signal. The pull-up circuit includes a dual-gate transistor. A first gate of the dual-gate transistor is electrically coupled to the control signal, a second gate of the dual-gate transistor is electrically coupled to a predetermined voltage, the source/drain of the dual-gate transistor serves as an output terminal for the gate pulse signal, and the drain/source of the dual-gate transistor is electrically coupled to the clock signal. The pull-down circuit pulls a potential at the first gate and another potential at the output terminal down to a power supply potential during the pull-up circuit is disabled.

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Hsin-Chu, Taiwan

Chen-Yi Wu