National Yang Ming Chiao Tung University

Taiwan Semiconductor Manufacturing Comp. Ltd.

Winbond Electronics Corporation

National Science Council of R.o.c.

Macronix International Co., Ltd.

Novatek Microelectronics Corp.

National Science Council

Silicon Integrated Systems Corporation

Tfl Lan Inc.

Chen-Yi Lee

Hsie-Chia Chang

Chien-Ching Lin

Chen-Hua Douglas Yu

Chen-Nan Yeh

Cheng-Hung Chang

Shih-Ting Hung

Clement Hsingjen Wann

Liang-Gi Yao

Jeff J Xu

Chun-Hu Cheng

Kelvin Yi-Tse Lai

Chih-Hao Liu

Alexander Kalnitsky

Shih-Fen Huang

Yu-Chang Jong

Yu-Rung Hsu

Mohammad Al-Shyoukh

Pei-Lun Wang

Sheng-Fu Hsu

Dah-Chuen Ho

Hsi-Chia Chang

Yi-Min Lin

Yun-Sheng Chan

Chien-Ying Yu

Chun-Yuan Yu

Yarsun Hsu

Jui-Yuan Yu

Szu-Chi Chung

Sung-Shine Lee

Yar-Sun Hsu

Yu-Tao Yang

Pao-Lung Chen

Terng-Yin Hsu

Wei-Hao Sung

Lin-Yu Huang

Chia-Lin Hsu

Chiu-Hua Chung

Yen-Chin Liao

Yi-Cheng Chiu

Hung-Ta Pai

Yu-Lin Tsai

Wei Ying Chiang

Chih-Hsiang Hsu

Fan-Ming Kuo

Ming-Wei Lai

Chi-Heng Yang

Shih-Fan Chen

Chung Cheng Wang

Jer-Min Tsai

Tzu-Yun Huang

Eugene Eu Tzuan Lee

Shu-Ping Lin

Lin-Hung Lai

Wen-Yue Lin

Ming-Che Lee

Chia-Jung Yu

Chen-Fong Hsiao

Yuan Chen

Juinn-Ting Chen

Po-Wen Hsieh

Cheng-Chi Wong

Yung-Yu Lee

Jr-Hau Lu

Hsi-Hao Huang

Ching-che Chung

Chia-Cho Wu

Cheng-Hsien Chen

Lin-Tien Mei

Tien-Sheng Lin

Zih-Cheng He

Bai-Jue Shieh

Yu-Chi Kao

The present inventive concept provides a capacitance sensor array chip with programmable fusion pixels comprising: a programmable module for generating a choosing signal according to a first clock signal; a delay pulse module for generating a third clock signal according to a second clock signal and a sensing pulse signal; and multiple electrode array modules comprising a charging unit for generating a charging signal according to the sensing pulse signal; M×N electrode pixel units forming an array, wherein the electrode arrays chooses a certain pattern of the electrode units according to the choosing signal in orders and the certain pattern of the electrode units in the electrode array generates a sampling signal according to the charging signal; and a sampling unit for generating a sensing output signal according to the sampling signal and the third clock signal.

Capacitance sensor array chip with programmable fusion pixels, sampling device thereof and controlling system thereof

A semiconductor ESD protection device includes a pair of source regions, a pair of gate structures, a drain region, a plurality of first conductive contacts, a plurality of second conductive contacts, a plurality of third conductive contacts, and a dummy structure. The pair of gate structures are disposed between the pair of source regions and extend along a direction. The drain region is disposed between the pair of gate structures. Each of the first conductive contacts is disposed on one of the pair of source regions and is arranged along the direction. Each of the plurality of second conductive contacts is disposed on one of the pair of gate structures. The plurality of third conductive contacts are disposed on the drain region and arranged along the direction. The dummy structure is disposed over the drain region and between the gate structures and between the third conductive contacts.

Semiconductor electrostatic discharge protection device

A microelectrode device, microfluidic chip, and microfluidic examination method are provided. The microfluidic chip includes a top plate and a microelectrode dot array having several microelectrode devices. Each microelectrode device includes a microfluidic electrode, heating electrode, and control circuit. The control circuit includes a microfluidic control and location sensing circuit, storage circuit, and temperature control circuit. The microfluidic control and location sensing circuit moves a sample within an enabling period of a microfluidic control signal and detects a capacitance value between the microfluidic electrode and the top plate within an enabling period of a location control signal. The storage circuit outputs the capacitance value, reads in the sample operation setup, and reads in the heating control setup within different enabling periods of the clock. The temperature control circuit determines either on or off according to the heating control setup within an enabling period of a heating control signal.

Microelectrode device, microfluidic chip, and microfluidic examination method

A microfluidic test system and method are provided. The microfluidic test system includes a control apparatus and a microfluidic chip. The control apparatus stores a test protocol of a biomedical test. The microfluidic chip includes a top plate and a microelectrode dot array having a plurality of microelectrode devices connected in series. The control apparatus provides a location-sensing signal to the microfluidic chip so that each microelectrode device detects a capacitance value between the top plate and the corresponding microfluidic electrode accordingly. The control apparatus provides a clock signal to the microfluidic chip so that each microelectrode device outputs the corresponding capacitance value accordingly. The control apparatus determines the size and location of a test sample within the microfluidic chip, generates a control signal according to the test protocol, the size, and the location, and provides the control signal to the microfluidic chip.

Microfluidic test system and microfluidic test method

A portable video display apparatus that adopts a L-layer processing architecture and performs the following operations for each layer of xlayer to xlayer: generating an optical flow map between a first and a second image frames, generating a primary rectified feature map according to a first feature map of the first image frame and the optical flow map, generating an advanced rectified feature map according to the optical flow map, the primary rectified feature map, and a second feature map of the second image frame, and generating a second feature map for the next layer according to the second feature map and the advanced rectified feature map. The portable video display apparatus generates an enlarged image frame by up-sampling the second image frame, generates a display image frame according to the second feature map at the x1layer and the enlarged image frame and displays it.

Video display systems, portable video display apparatuses and video enhancement methods

An image sensor chip with depth information is provided. The image sensor chip includes an SPAD array, a time-to-digital converter module, a storage circuit, and a data processing circuit. The SPAD array includes a plurality of image sensor units, and each of the image sensor units includes a plurality of SPAD units and a decision circuit, wherein each of the SPAD units outputs a photon detection result within a scan period, and the decision circuit generates an image-sensing signal based on the photon detection results. The time-to-digital converter module generates a plurality of first time data in response to the image-sensing signals. The storage circuit stores the first time data temporarily. The data processing unit reads the first time data from the storage circuit and generates a plurality of second time data in response to the first time data.

Image sensors chip with depth information

The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

Low-k dielectric damage prevention

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a source region and a drain region in a substrate, a gate structure and a metallic line. The source region surrounds the drain region in the substrate. The gate structure is disposed on the substrate, and disposed between the source region and the drain region. The gate structure surrounds the drain region. The metallic line is located above the source and drain regions and the gate structure and electrically connected to the drain region or the source region. The source region includes a doped region having a break region located between two opposite ends of the doped region. The metallic line extends from the drain region, across the gate structure and across the break region and beyond the source region.

Semiconductor device with ring-shaped doped region and manufacturing method thereof

A substitute box includes a target input terminal, an obfuscation input terminal, a first output terminal and a second output terminal. The target input terminal is configured to receive a target input data. The obfuscation input terminal is configured to receive an obfuscation input data unrelated to a plaintext. The first output terminal is configured to output a first output data. The second output terminal is configured to output a second output data associated with the first output data. The first output data and the second output data are generated according to both the target input data and the obfuscation input data.

Substitute box, substitute method and apparatus thereof

A motion detecting device includes an accelerometer configured to generate gravitational acceleration readings associated respectively with consecutive time segments, an angular acceleration sensor and configured to generate angular acceleration readings, and a processor operable in one of a standby mode and an active mode. When operated in the standby mode, the processor activates the accelerometer, deactivates the angular acceleration sensor, and determines whether the user is in a substantial moving state. When determined that the user is in the substantial moving state, the processor switches to the active mode to activate both the accelerometer and said angular acceleration sensor, in order to determine the motion of the user.

Motion detecting device, motion detecting sensor unit and motion detection method

An encryption/decryption apparatus and a power analysis protecting method thereof are provided. The encryption/decryption apparatus adapted to perform encryption/decryption operation on digital data includes a data encryption/decryption unit, a random number generator, and a power analysis protecting circuit. The data encryption/decryption unit receives the digital data and performs an encryption/decryption operation on the digital data. The random number generator is used to generate random number data, the random number data has N bits, and N is a positive integer. The power analysis protecting circuit generates M kinds of power signals having different levels according to each bit data of the random number data when the random number data is received by the power analysis protecting circuit, and M is equal to the Npower of 2.

Encryption/decryption apparatus and power analysis protecting method thereof

A semiconductor device includes a first a first transistor configured to operate at a first threshold voltage level. The first transistor includes a first gate structure and a first drain terminal electrically coupled to the first gate structure. The semiconductor device also includes a second transistor configured to operate at a second threshold voltage level different from the first threshold voltage level. The second transistor includes a second source terminal and a second gate structure electrically coupled to the first gate structure. The first gate structure and the second gate structure comprise a first component in common, and the second gate structure further includes at least one extra component disposed over the first component. The number of the at least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Semiconductor device structure and manufacturing method thereof

A cracking method for cracking a secret key of an encrypting device includes: building up a leakage model for the encrypting device; performing a mathematical calculation on the leakage model, according to a plurality of sets of input data, to generate a mathematical model; generating a plurality of sets of hypothesized keys; generating a plurality of sets of simulation data corresponding to the hypothesized keys using the mathematical model; providing the input data for the encrypting device and detecting a plurality of sets of leakage data generated by the encrypting device; performing the mathematical calculation on the leakage data to generate calculated data; determining a correlation between each of the simulation data and the calculated data; and determining one of the hypothesized keys to be consistent with the secret key according to the correlation.

Cracking devices and methods thereof

A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Dielectric punch-through stoppers for forming FinFETs having dual Fin heights

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first transistor configured to include a first threshold voltage level. The first transistor includes a gate structure. The gate structure includes a first component including a first conductive type. A second transistor configures to include a second threshold voltage level different from the first threshold voltage level. The second transistor includes a gate structure. The gate structure includes a second component including the first conductive type. At least one extra component is disposed over the second component. The least one extra component includes a second conductive type opposite to the first conductive type. The first transistor and the second transistor are coupled such that the number of the least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Growing community of inventors

Hsinchu, Taiwan

Chen-Yi Lee