Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen Yen-Huei

Hung-Jen Liao

Jui-Jen Wu

Yung-Lung Lin

Dao-Ping Wang

Kun-Lung Chen

Kun Lung Chen

Some embodiments regard a method comprising: controlling a row of cells of a memory array with a first signal; controlling a column of cells of the memory array with a second signal; transferring data from a cell activated by both the first signal and the second signal to a pair of bit lines associated with the cell; and using the data from the pair of bit lines as read data and as data written back to the cell to ensure the cell stores valid data.

Memory array with corresponding row and column control signals

A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.

Power switching circuit

A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.

Dynamic power control for expanding SRAM write margin

A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

Growing community of inventors

Hsinchu, Taiwan

Chen Yen-Huei