United Microelectronics Corp.

International Business Machines Corporation

Hsing Chau Industrial Co., Ltd.

Chen-Wei Lee

Ming-Hui Pan

Shih-Chen Chang

Chih-Pao Chang

Marcus A Kelly

Yu-Chen Kung

Guo-Sheng Mo

Su-Jen Tsai

Chun-Hsien Huang

Kuan-Cheng Su

Wen-Jung Liao

Chun-Ming Chang

Chun-Liang Hou

Meng-Jin Tsai

Cheng-Han Huang

Huan-Ting Tseng

Te-Chuan Liao

Hung-Chin Huang

A method for controlling a fan is described and includes controlling a rotation speed of a fan according to a first rotation speed time-variable rate by a controller, and controlling the rotation speed of the fan according to a second rotation speed time-variable rate by the controller in response to a change in an operating parameter of a target device, where the fan and target device are for use in a computer system.

Fan control of a computer system based on power ratio

A fan control system for a computer system is provided. The computer system includes a fan and a target device. The fan control system includes a controller to control the rotation speed of the fan. The controller determines a time-variable rate of the rotation speed according to an operating parameter of the target device. Particularly, the controller determines the time-variable rate of the rotation speed according to a ratio of the consumed power to the rated power of the target device. Alternatively, the controller can determine the rotation speed according to the ratio of the consumed power to the rated power of the target device.

The invention provides a thermal uniformity compensating method and apparatus. The steps of the method includes: respectively measuring a plurality of first resistances of a plurality of hot spot patterns of a chip over an hot spot effect, wherein a plurality of pattern densities of the hot spot patterns are different; respectively measuring a plurality of second resistances of each of the hot spot patterns of the chip by a plurality of test keys over the hot spot effect, wherein a plurality of distances between the test keys and the corresponding hot spot pattern are different; establishing a look-up information according to the first and second resistances; analyzing a layout data of the chip for obtaining a pattern density information; and generating a calibrated layout data according to the pattern density information and the look-up information.

Thermal uniformity compensating method and apparatus

A method of manufacturing doping patterns includes providing a substrate having a plurality of STIs defining and electrically isolating a plurality of active regions in the substrate, forming a patterned photoresist having a plurality of exposing regions for exposing the active regions and the STIs in between the active regions on the substrate, and performing an ion implantation to form a plurality of doping patterns in the active regions.

Method of manufacturing doping patterns

A telecommunication connector includes a front holder having a plug port at the front and a press plate at the rear, a rear holder coupled to the rear of the front holder, a support member disposed at the front of the rear holder and extended to the top of the plug port, two rows of terminals installed at the rear holder, a flexible circuit board bent into the electric connecting plate and the extension plate, a curved portion wound across the front of the support member of the rear holder, such that the electric connecting plate is passed through the bottom of the support member and entered into the top of the plug port, and a fixing plate separately bent at rear ends of the electric connecting plate and the extension plate and pushed to the front of the rear holder by the press plate and coupled to the terminals.

Telecommunication connector having a flexible circuit board wound across a support member and ends being bent into fixing plates coupled to two rows of terminals

A method for forming a double spacer structure comprising the steps of first providing a semiconductor substrate that has a first gate and a second gate already formed thereon, wherein the gate length of the second gate is greater than the gate length of the first gate. Then, a first insulating layer is formed over the substrate and the gates. Next, a photoresist layer is formed over the first insulating layer above the second gate while exposing the first insulating layer above the first gate. Subsequently, a first etching operation is performed to establish a first spacer structure along the sidewalls of the first gate, and then the photoresist layer is removed leaving the first insulating layer over the second gate. Thereafter, a second insulating layer is formed over the substrate, the first gate and the first insulating layer, and then a second etching operation is performed to establish a second spacer structure along the sidewalls of the second gate. Therefore, a second spacer that has a width greater than the first spacer does is finally obtained.

Manufacturing method of double spacer structure for mixed-mode IC

A semiconductor fabrication method that enhances the ESD (electrostatic discharge) protection capability of an ESD protective device provided in an integrated circuit such as a mask-programmed ROM, allows the mask-programmed ROM to be downsized while still providing adequate ESD protection capability, and allows the mask-programmed ROM to be fabricated in a smaller size, while nonetheless providing adequate ESD protection capability for the internal circuit. Initially, a mask for the ion implantation process for the ROM is prepared. The mask is patterned additionally with a plurality of strips used to define breakdown voltage controlling areas in the ESD protective device. Then, the ion implantation process is performed through the mask so as to form the breakdown voltage controlling areas each beneath the drain of the n-type CMOS transistor. The breakdown voltage controlling areas are heavily doped, thereby reducing the breakdown voltage at the junction between the drain and the p-well in the n-type CMOS transistor. This enhances the ESD protection capability of the integrated circuit.

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Taipei, Taiwan

Chen-Wei Lee