Powerchip Semiconductor Manufacturing Corporation

Chen-Tso Han

Shih-Ping Lee

Po-Yi Wu

Bo-An Tsai

Yu-An Chen

Shih-Siang Chen

Yi-Nung Lin

A memory structure including first and second transistors, an isolation structure and a capacitor and a manufacturing method thereof are provided. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extensions are extended from the body portion into the substrate at two sides of the isolation structure and connected to the source/drain regions of the first and the second transistors, respectively. The widths of first and second extension portions are decreased downward from a top surface of the isolation structure.

Growing community of inventors

Taipei, Taiwan

Chen-Tso Han