Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Ting Lin

Chih-Hung Wu

Chih-Cheng Chou

Chia-Hua Chang

Mei-Yen Li

Fu-Sheng Lee

Chien-Chen Chen

Cheh-Chieh Lu

The present disclosure provides a system and method for recognizing a defect image associated with a semiconductor substrate. In one example, the method includes collecting defect data of the defect image by testing and measuring the semiconductor substrate, extracting a pattern from the defect data, normalizing a location, orientation, and size of the pattern, and identifying the pattern after the pattern is normalized.

Translation engine of defect pattern recognition

A yield analysis method. First, a wafer having multiple dies is inspected to obtain wafer defect data containing defect information for every die in the wafer. Then a wafer map and an overall yield are generated according to the wafer defect data. The wafer map displays defective dies and defect-free dies in the wafer. Then, first and second systematic limited yields are calculated in accordance with the wafer defect data and the wafer map, wherein the first systematic limited yield is calculated excluding defective dies with localized distribution, and the second systematic limited yield is calculated excluding defective dies with repeated distribution. Then a random defect limited yield is determined in accordance with the overall yield, the first systematic limited yield, and the second systematic limited yield.

Yield analysis method

A method for forming copper interconnects, without inducing copper diffusion, by eliminating the copper chemical-mechanical polishing process. A semiconductor structure is provided having a first metal layer thereover. A first inter-metal dielectric layer is formed over the first metal layer and planarized. A first resist layer is formed over the first inter-metal dielectric layer, and the first resist layer and the first inter-metal dielectric layer are patterned to form via openings with the first metal layer forming the bottoms of the via openings. A barrier/seed layer, comprising a barrier layer and an overlying seed layer, is formed on the sidewalls and bottoms of the via openings. A self-align layer, composed of a high-resistivity, inorganic material, is formed over the barrier/seed layer. The self-align layer is patterned to reform the via openings and to form trench openings, exposing the barrier/seed layer on the bottoms and sidewalls of the via openings and on the bottoms of the trench openings. A copper layer is electroplated onto the exposed barrier/seed layer at the bottoms and sidewalls of the via openings and on the bottom of the trenches. The remaining portions of the self-align layer removed, then the exposed portions of the barrier/seed layer are removed.

Method for processing and integrating copper interconnects

Growing community of inventors

Hsinchu, Taiwan

Chen-Ting Lin