Faraday Technology Corporation

Chen-Teng Fan

Cheng-I Huang

Wang-Jin Chen

Jyh-Herng Wang

Yu-Wen Tsai

Ya-Yun Liu

Jyh-Herny Wang

Peng-Chuan Huang

An I/O circuit placement method. In the I/O circuit placement method, at least two rows of I/O circuits are placed on a first side of the chip, and each I/O circuit has a head section and a tail section. The placement direction of the head section and the tail section is perpendicular to the placement direction of the I/O circuits in the rows. The semiconductor further has a core circuit disposed on the chip, wherein the rows of I/O circuits are disposed outside the core circuit and are at the periphery of the chip. Due to the I/O circuit placement in the semiconductor device, the present invention reduces the area of the semiconductor chip and fabrication cost.

I/O circuit placement method and semiconductor device

A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.

Memory test system for peak power reduction

A mux scan cell includes a multiplexer having a first input node for receiving raw data, a second input node for receiving test data, an output node, a selection node, and a delay circuit electrically connected between the second input node and the output node for prolonging a traveling time which the test data takes to travel from the second input node to the output node. The mux scan cell also includes a flip-flop connected to the multiplexer. With the delay circuit, the traveling time of the test data is prolonged such that the traveling time which the test data takes to travel from the second input node to the output node simulates a sum of a traveling time in which the raw data travels through a combinational logic and a traveling time in which the raw data travels from the first input node to the output node.

Mux scan cell with delay circuit for reducing hold-time violations

A silicon chip capacitance measurement circuit including three pairs of completely matched MOS transistors divided into two symmetrical circuits. Capacitance of a capacitor within the silicon chip is measured using the difference in average charging current flowing from the measurement circuit via a left and a right capacitor. A power supply provides a constant voltage source to the measurement circuit. A current measuring device measures the current flowing from the power supply to the measurement circuit. A signal generator provides a group of three-phase non-overlapping signals to the measurement circuit. The capacitance measurement circuit is able to limit measurement error due to the return of different size negative currents leading to the transient switching of MOS transistors in the current measurement device so that accuracy of capacitance measurement improves.

Chip capacitance measurement circuit

A clock architecture including a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit block. The clock source generates a global clock signal, which is then transferred to the multi-phase clock signal generator connected to the clock source. Upon receipt of global clock signal, the multi-phase clock signal generator, which is connected to a control bus, generates clock signals of different phases according to the signals from the control bus. Each of the clock signal branches transfers one of the clock signals of different phases, wherein each of the clock signal branches is individually connected to the circuit block through an electrical switch. Only one switch is at an on state at one time, so that the clock signal of a corresponding phase is transferred to the circuit block. The driving forces applied on the clock buffer connected to the clock source and the clock buffers on the branches are adjustable for reducing clock skew. Alternately, programmable delay buffers can be used for achieving the same goal.

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Hsinchu, Taiwan

Chen-Teng Fan