Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Shien Chen

Tin-Hao Kuo

Ching-Wen Hsiao

Chen-Cheng Kuo

Chita Chuang

Chih-Hua Chen

Yao-Chun Chuang

Sheng-Yu Wu

Mirng-Ji Lii

Hon-Lin Huang

Yen-Liang Lin

Chin-Yu Ku

Chen-Hua Douglas Yu

Ming-Da Cheng

Ming Hung Tseng

Yu-Feng Chen

Kuo-Ching Hsu

Wei-Li Huang

Hao-Juin Liu

Chung-Shi Liu

Kuo-Chio Liu

Kai-Ming Ching

Yu-Wei Lin

Yi-Jen Lai

Ming-Fa Chen

Chih-Horng Chang

Hsi-Kuei Cheng

Wei Sen Chang

Chih-Wei Lin

Tsung-Ding Wang

Guan-Yu Chen

Chang-Chia Huang

Hsiu-Jen Lin

Tsung-Shu Lin

Yu-Chih Huang

Kuo Lung Pan

Yu-min Liang

Wei-Hung Lin

Tzuan-Horng Liu

Chin-Fu Kao

Tsung-Hsien Chiang

Wen-Hsiung Lu

Chung-Yi Lin

Yu-Huan Chen

Chih-Hung Su

Ming-Chih Yew

Chien-Chih Chou

Chien-Hsiun Lee

Yu-Chen Hsu

Jiun Yi Wu

Han-Ping Pu

Pei-Haw Tsao

Hui-Min Huang

Chun-Jen Chen

Wen-Yi Lin

Kuang-Chun Lee

Wen-Chih Chiou

Chien Ling Hwang

Chih-Fan Huang

Sey-Ping Sun

En-Hsiang Yeh

Hung-Pin Chang

Cheng-Hung Chen

Monsen Liu

Li-Huan Chu

Yang-Che Chen

Bo-I Lee

Shin-Puu Jeng

Shang-Yun Hou

Wei-Cheng Wu

Ying-Ching Shih

Chien-Li Kuo

Chun-Hung Lin

Chun-Cheng Lin

Kuei-Wei Huang

Tsung-Fu Tsai

Yu-Min Liang

Sen-Kuei Hsu

Yian-Liang Kuo

Kuo-Chin Chang

Hua-Shu Ivan Wu

Clinton Chao

Han-Liang Tseng

Hua-Wei Tseng

Dun-Nian Yaung

Jen-Cheng Liu

Szu-Wei Lu

Po-Hao Tsai

Chien-Hsun Lee

Shou-Gwo Wuu

Hsin-Chieh Huang

Mill-Jer Wang

Hao Chen

Szu Wei Lu

Kuo-Lung Pan

Hong-Seng Shue

Cheng-Hung Tsai

Kai-Hsiung Chen

Yu-Jen Cheng

Ying-Jui Huang

A chip package structure is provided. The chip package structure includes a first wiring substrate comprising a substrate, a first pad, a second pad, and an insulating layer. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, the first surface is opposite to the second surface, the insulating layer is over the first surface and partially covers the first pad, and the first pad is wider than the second pad. The chip package structure includes a nickel-containing layer over the first pad. The chip package structure includes a conductive protection layer over the nickel-containing layer. The conductive protection layer has a curved surface, and a recess is surrounded by the curved surface and an inner wall of the insulating layer over the first pad.

Chip package structure with metal-containing layer

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element partially covering the magnetic element. The semiconductor device structure further includes a conductive feature over the isolation element.

Semiconductor device structure with magnetic element

In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

Semiconductor device and method

A semiconductor device structure is provided. The semiconductor device structure includes a first conductive line over a substrate. The semiconductor device structure includes a first protection cap over the end portion. The first protection cap and the first conductive line are made of different conductive materials, and the first protection cap exposes a peripheral region of a top surface of the end portion. The semiconductor device structure includes a first photosensitive dielectric layer over the substrate, the first conductive line, and the first protection cap. The semiconductor device structure includes a conductive via structure passing through the first photosensitive dielectric layer and connected to the first protection cap.

Semiconductor device structure with a protection cap at an end portion of a conductive line

A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.

Lthc as charging barrier in info package formation

A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

Semiconductor device with discrete blocks

A substrate for a semiconductor package includes an array of bonding pads on a first surface of the substrate, and a plurality of raised structures adjacent to at least some of the bonding pads on the first surface of the substrate. The raised structures may be configured to control the height of solder balls contacting the array of bonding pads when the package substrate is mounted onto a support substrate. The raised structures may compensate for a deformation of the package substrate so that the co-planarity of the solder balls may be improved, thereby providing an improved solder connection between the package substrate and the support substrate.

Systems for semiconductor package mounting with improved co-planarity

In an embodiment, a device includes: a dielectric layer over an active surface of a semiconductor substrate; a conductive via in the dielectric layer, the conductive via including a first copper layer having a non-uniform grain orientation; and a bonding pad over the conductive via and in the dielectric layer, the bonding pad including a second copper layer having a uniform grain orientation, a top surface of the bonding pad being coplanar with a top surface of the dielectric layer.

Die bonding pads and methods of forming the same

According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Substrate and package structure

A package structure is provided. The package structure includes a substrate, a cover element, a semiconductor device, a protruding element, an adhesive element, and an electrical connector. The cover element is disposed on the substrate and having a recess. The semiconductor device is disposed on the substrate and disposed in the space surrounded by the cover element. The protruding element extends from the substrate and disposed in the recess. The adhesive element is disposed in the recess. The electrical connector is in contact with the substrate and the semiconductor device.

Semiconductor package structure having ring portion with recess for adhesive

A method of forming a semiconductor device includes following steps. A first organic layer is formed to cover a first conductive layer. A first opening is formed in the first organic layer to expose a first surface of the first conductive layer. A first silicon layer is formed on a sidewall of the first opening and the first surface of the first conductive layer. A first dielectric layer is formed on the sidewall of the first opening and the first surface of the first conductive layer over the first silicon layer. By using a first mask, portions of the first silicon layer and the first dielectric layer on the first surface are simultaneously removed to expose the first surface, wherein after removing the portions of the first silicon layer and the first dielectric layer, the first dielectric layer covers a top surface of the first silicon layer.

Method of forming semiconductor device

A semiconductor package includes a substrate, a package structure, a lid structure, and a thermal spreader layer. The package structure is disposed on the substrate, wherein the package structure includes a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies. The lid structure is disposed over substrate and covering the package structure. The thermal spreader layer is disposed between the lid structure and the package structure, wherein the thermal spreader layer has a profile that is discontinuous in thickness at a gap region corresponding to the gap.

Semiconductor package and method of manufacturing semiconductor package

A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a nickel layer over the first pad. The nickel layer has a T-shape in a cross-sectional view of the nickel layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip.

Chip package structure with nickel layer

A package structure is provided. The package structure includes a substrate and a chip-containing structure over the substrate. The package structure also includes a protective lid attached to the substrate through a first adhesive element and a second adhesive element. The first adhesive element has a first electrical resistivity, and the second adhesive element has a second electrical resistivity. The second electrical resistivity is greater than the first electrical resistivity. The second adhesive element is closer to a corner edge of the substrate than the first adhesive element, and a portion of the second adhesive element is between the first adhesive element and the chip-containing structure.

Package structure with protective lid

A semiconductor device package is provided, including a package substrate, a semiconductor device, a metal lid, and a metal thermal interface material (TIM). The package substrate has a first surface. The semiconductor device is disposed over the first surface of the package substrate. The metal lid is disposed over the semiconductor device and the package substrate. The metal TIM is interposed between the metal lid and the top surface of the semiconductor device for bonding the metal lid and the semiconductor device. A shape of the lateral sidewall of the metal TIM in a longitudinal section is concave arc, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device.

Semiconductor device package having metal thermal interface material

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Zhubei, Taiwan

Chen-Shien Chen