Other

Realtek Semiconductor Inc.

Hangzhou Haicun Information Technology Co., Ltd.

Microsoft Technology Licensing, LLC

Xiamen Haicun IP Technology LLC

Chen Shen

Guobiao Zhang

Neng-Hsien Lin

Kai Liu

Jinfeng Kang

Bo Wu

Hongyu Yu

Kai-Yuan Yin

Bin Yu

Congyu Zhang

Chenchang Zhan

Bhaskardeep Khaund

XiangDong Lu

XuGuang Wang

DongYun Zhang

Ming-Chang Wu

Yong-Fei Li

Yiqun Wang

Yao Feng

Ti-Ti Chen

Haichao Zheng

Wei Qian

Guobing Jiang

RangYu Deng

An orchestration engine intermittently scans secrets, of different secret types, to identify secrets that are to be rotated. The orchestration engine calls an application programming interface (API) exposed by a serverless management system and wakes up the serverless management system. The serverless management system generates a new secret, stores the new secret for rotation, and interacts with a dependent system in order to revoke an old secret and implement the new secret. Once the secret is rotated, and the new secret is implemented, the orchestration engine stores the new secret in a secret store.

Lifecycle management of secrets on serverless platform

A three-dimensional processor (3D-processor) for parallel computing includes a plurality of computing elements. Each computing element comprises at least a three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Deficiency in latency is offset by a large scale of parallelism.

Three-dimensional processor for parallel computing

A cable includes a first plug, a second plug, and a controller. The first plug is configured to be connected with a host. The second plug is configured to be connected with a device. The controller is coupled between the first plug and the second plug, and is configured to monitor a connection message transferred between the host and the device, and to determine, according to the connection message, a transfer mode that the host and the device is to enter, and to set a plurality of electrical parameters to be a corresponding one set in a plurality of sets of predetermined parameters.

Cable, controller, and control method

Disclosed is a method for a USB power receiving device selecting a power supply option. The method is performed by the USB power receiving device and includes: receiving N power data object(s) (PDO(s)) from a USB power supplying device, in which the N is a positive integer; checking whether at least one of M PDO(s) of the USB power receiving device matches at least one of the N PDO(s) according to a selection rule including a voltage requirement and a current-related requirement and accordingly generating a request data object (RDO), in which the M is a positive integer; and transmitting the RDO to the USB power supplying device to request the USB power supplying device to supply power to the USB power receiving device according to the RDO.

Method for USB power receiving device selecting power supply option

A three-dimensional processor (3D-processor) for calculating mathematical functions in parallel, comprises a larger number (e.g. at least one thousand) of computing elements, with each computing element comprising at least one three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Even though each individual 3D-M cell is slower than a conventional two-dimensional memory (2D-M) cell, this deficiency in speed is offset by a significantly larger scale of parallelism.

Processor for calculating mathematical functions in parallel

A transmission interface communicating method used in a display device that includes the steps outlined below is provided. A first status update signal is received from a host device to turn a hot plug detect (HPD) status of the display device to a high status. A HPD signal having a low status is transmitted to the host device in response to the first status update signal. A configuration signal is received from the host device. A configuration acknowledgement signal is transmitted to the host device in response to the configuration signal. The HPD signal having the high status is actively transmitted to the host device.

Transmission interface communicating method and connection interface

The present invention discloses a processor comprising three-dimensional memory (3D-M) array (3D-processor). Instead of logic-based computation (LBC), the 3D-processor uses memory-based computation (MBC). It comprises an array of computing elements, with each computing element comprising an arithmetic logic circuit (ALC) and a 3D-M-based look-up table (3DM-LUT). The ALC performs arithmetic operations on the LUT data, while the 3DM-LUT is stored in at least one 3D-M array.

Processor comprising three-dimensional memory (3D-M) array

An SSIC (SuperSpeed Inter-Chip) device comprises a detecting circuit operable to execute at least one of a first and a second detection processes and generate a detection result, wherein the first detection process is operable to detect an SSIC compatible object and the second detection process is operable to detect whether the SSIC compatible object satisfies at least one of a de-link state and a re-link state, a control circuit operable to generate a control signal according to the detection result, and a Mobile-Physical-Layer circuit operable to execute at least one of the following steps: if the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, disconnecting a normal connection between the SSIC device and the SSIC host; and if the control signal indicates that the SSIC compatible object is detected and satisfies the re-link state, connecting the SSIC device with the SSIC host.

SSIC device and link control method for SSIC device

The present invention discloses a three-dimensional one-time-programmable memory (3D-OTP) comprising an off-die address/data-translator (A/D-translator). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an A/D-translator of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The A/D-translator converts at least an address and/or data between logic and physical spaces.

Three-dimensional one-time-programmable memory comprising off-die address/data-translator

Growing community of inventors

Suzhou, China

Chen Shen