Macronix International Co., Ltd.

Chen-Shang Lai

Tao-Cheng Lu

Shin Su

Meng-Huang Liu

Mam-Tsung Wang

Meng-Hwang Liu

The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Silicon controlled rectifier structure with guard ring controlled circuit

An electrostatic discharge protection which is electrically coupled with an interface terminal and a devices area, at least include a first bipolar junction transistor, a second bipolar junction transistor, a first MOS transistor, and a second MOS transistor. Both bipolar junction transistors forms the well-known silicon controlled rectifier, first MOS transistor locates between interface terminal and second bipolar junction transistor and second MOS transistor locates between emitter of second bipolar junction transistor and ground point, and gates of both MOS transistor electrically coupled with voltage base point whose voltage is equal to work voltage of devices area. While devices area is turned off, silicon controlled rectifier would be latch-up and provides function of electrostatic discharge protection. While devices area is turned on, second MOS transistor also is turned on so that part of current flows into ground point but not flows into second bipolar junction transistor. Thus, positive feedback between two bipolar junction transistors is reduced and then latch-up is eliminated.

Electrostatic discharge protection circuits with latch-up prevention function

A self-protected output driver for an integrated circuit utilizing cascode configured MOSFET transistors is formed in a single active region, allowing a smaller layout area without sacrificing performance. Furthermore, the driver is laid out according to a standard cell layout and is adaptable for a variety of output driving specifications according to the need of a particular implementation. A doped region having a first conductivity type is formed in the substrate. A plurality of sets of cascode connected transistors having channels in the doped region is included. Sets of cascode connected transistors in the plurality include a first diffusion region, a second diffusion region on a first side of and separated from the first diffusion region by a channel of a first transistor, a third diffusion region on a second side of and separated from the first diffusion region by a channel of the second transistor, a fourth diffusion region on a first side of and separated from the second diffusion region by a channel of a third transistor, a fifth diffusion region on a second side of and separated from the third diffusion region by a channel of a fourth transistor. Gate structures are formed over the channels of the first, second, third and fourth transistors. An interconnect structure couples the first diffusion region to the contact pad, the fourth and fifth diffusion regions to the second supply terminal, the gate structures of the first and second transistors to a first supply terminal, the gate structure of the third transistor to a selected one of the second supply terminal and a signal source, and the gate structure of the fourth transistor to a selected one of the signal source and the second supply terminal. The structure acts typically as a pull-down stage for an output driver on an integrated circuit. A pull-up transistor is included in the complete circuit. The diffusion regions between the first and third transistor and between the second and fourth transistor are formed without silicide.

Growing community of inventors

Taichung, Taiwan

Chen-Shang Lai