Kingpak Technology Inc.

Other

Chen Pin Peng

Nai Hua Yeh

Jichen Wu

Chung Hsien Hsin

Hsiu Wen Tu

Mon Nan Ho

Chief Lin

Wei Ling Chang

Allis Chen

Meng Ru Tsai

Jason Chuang

Yves Huang

Pierre Liu

Fu Yung Huang

Wu Hsiang Lee

May Chen

Kuang Yu Fan

Ching-Shui Cheng

C S Cheng

Ren Long Kau

Chih Hsien Chung

An image sensor module with air escape hole includes a substrate having an upper surface and a lower surface. A chip is mounted on the upper surface of the substrate. A plurality of wires are electrically connected the chip to the upper surface of the substrate. An adhered layer is coated on the upper surface of the substrate. A lens holder is mounted on the upper surface of the substrate by the adhered glue, and formed with a top wall, a lateral wall, and an internal thread, wherein the top wall is formed with an air escape hole. A lens barrel is formed with an external thread screwed on the internal thread of the lens holder. And a filled glue is filled within the air escape hole of the lens holder.

Image sensor module with air escape hole and a method for manufacturing the same

An image sensor module with a protection layer and a method for manufacturing the same includes a substrate with an upper surface and a lower surface, a chip is mounted on the upper surface of the substrate, a plurality of wires are electrically connected the bonding pads of the chip to the first electrodes of the substrate, a adhered layer is coated on the upper surface of the substrate, a lens holder has a lateral wall, a protection layer and internal thread, the lateral wall is adhered on the upper surface of the substrate by the adhered layer to encapsulate the chip, so that the protection layer is located on adjacent the sensor region of the chip to prevent adhered layer flowed to the sensor region of the chip; and a lens barrel is formed with external thread screwed on the internal thread of the lens holder.

Image sensor module with a protection layer and a method for manufacturing the same

An integrated circuit package comprises a substrate having an upper surface, a lower surface, and a long slot penetrating from the upper surface to the lower surface. The lower surface is formed with a wiring regioins arranged at side of the long slot, and the wiring regions formed with a plurality of connection points. A glue layer is coated on the upper surface of the substrate and as arranged at the periphery of the long slot. The integrated circuit has a first surface formed with a plurality of bonding pads and is adhered to the glue layer. The wires, each of which is arranged within the long slot of the substrate electrically connected the bonding pads of the integrated circuit to the connection points of the substrate. The first compound layer is filled within the long slot of the substrate to protect the wires.

Integrated circuit package having a resistant layer for stopping flowed glue

A memory module structure of the invention is used for being assembled on a locking device. The memory module includes a substrate and a plurality of memories. The substrate has certain long sides and short sides. Notches are formed on the short sides for being secured by the locking device. Each of the plurality of memories has a suitable length and width. Some memories of the plurality of memories are transversely mounted on the substrate with respect to the substrate. The other memories of the plurality of memories are longitudinally mounted on the substrate with respect to the substrate. According to this structure, it is possible to suitably arrange a plurality of memories on the substrate so as to increase the memory capacity of the memory module.

Memory module structure

A package structure for an integrated circuit includes a substrate, an integrated circuit, an adhesive layer, a plurality of wirings, and a glue layer. The substrate has a first surface and a second surface. The first surface is formed with a plurality of signal input terminals. The second surface is formed with a plurality of signal output terminals for electrically connecting to the circuit board. The integrated circuit has a lower surface and an upper surface. Recesses are formed at two sides of the lower surface, and a plurality of bonding pads are formed on the upper surface. The adhesive layer is used for adhering the lower surface of the integrated circuit to the first surface of the substrate. The wirings are electrically connecting to the bonding pads of the integrated circuit and to the signal input terminals of the substrate. The glue layer is used for sealing the plurality of wirings and the integrated circuits. According to the structure, the problem caused by the overflowed glue in the integrated circuit can be effectively avoided. A method for manufacturing the structure is also disclosed.

Method for manufacturing a package structure of integrated circuits

A semiconductor package structure having central leads according to the invention includes a substrate, a semiconductor device, a plurality of wires, and glue. A long slot penetrating through the substrate is formed in the substrate. A plurality of bonding pads formed on the semiconductor device are mounted on substrate. The plurality of bonding pads on the semiconductor device are exposed via the long slot of the substrate. The length of the semiconductor device is smaller than that of the long slot of the substrate so that a channel is formed at one side of the long slot when the semiconductor device is mounted on the substrate. The plurality of wires are arranged within the long slot of the substrate for electrically connecting the plurality of bonding pads on the semiconductor device to the plurality of signal output terminals on the substrate. The glue is provided for sealing the upper surface of the substrate to protect the semiconductor device. The glue is poured into the long slot of the substrate via the channel formed by the long slot of the substrate, for covering the plurality of wires.

Semiconductor package structure having central leads and method for packaging the same

A stacked structure for memory chips includes a substrate, a lower memory chip, an upper memory chip, and an insulation medium. The substrate has an upper surface, a lower surface and a slot penetrating through the substrate from the upper surface to the lower surface. The lower memory chip has a central portion formed with a plurality of bonding pads. The lower memory chip is arranged on the upper surface of the substrate. The plurality of bonding pads is exposed via the slot of the substrate, and the bonding pads are electrically connected to the lower surface of the substrate via a plurality of wires. The upper memory chip has a central portion formed with a plurality of bonding pads. The upper memory chip is arranged on the lower memory chip in a back-to-back manner with respect to the lower memory chip so that the plurality of bonding pads of the upper memory chip faces upwards. The insulation medium has a central portion formed with a slot. The plurality of bonding pads of the upper memory chip is exposed via the slot of the insulation medium. The insulation medium is formed with a plurality of traces electrically connecting to the bonding pads of the upper memory chip and the upper surface of the substrate via a plurality of wires. Accordingly, the length and radian of each wire can be reduced so that a better signal transmission effect and a smaller package volume can be obtained.

Stacked structure for memory chips

An stacked structure of semiconductor means and method for manufacturing the same, comprises a substrate, a lower semiconductor chip, an adhered glue layer, a plurality of wires and an upper semiconductor chip. The adhered glue layer located between the substrate and the lower semiconductor to adhere the lower semiconductor to the substrate. The overflow glue of the adhered glue layer covered above the periphery of the lower semiconductor chip. The plurality of wires each being electrically connected to the lower semiconductor chip and the substrate, so that each wires are located above the overflow glue. The upper semiconductor chip is located above lower semiconductor chip and electrically connected to the substrate.

Growing community of inventors

Hsinchu Hsien, Taiwan

Chen Pin Peng