Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Peng Fan

Wen-Cheng Chien

Chi-Wen Liu

Jung-Chih Tsao

Hsien-Ping Feng

Steven Lin

Hui-Jen Chu

Chien-Chih Chou

Sheng-Yuan Lin

Jui-Ping Chuang

Po-Hsiung Leu

Ming-Yi Lin

Chen-Fa Lu

Shin-Yeu Tsai

Tien-Chen Hu

Wen-Kung Cheng

Ming-Shuo Yen

Ming-Hsien Chen

Kuo-Hsien Cheng

Chia-Ming Yang

Yao Hsiang Liang

Chao-Keng Li

Li-Ming Huang

Jung-Chen Yang

Tsang-Yu Liu

Richard Chen

Fang-Jen Hsu

Yun-Da Fan

Chi-Ping Chen

Wen-Yu Ho

Yong-Sin Chang

Labo Chang

Ming-Yuang Cheng

Si-Kwua Cheng

Si-Kua Cheng

Che-Tsao Wang

A semiconductor structure includes a transistor formed over a substrate. The transistor includes a transistor gate and at least one source/drain region. The semiconductor structure includes a pre-determined region coupled to the transistor. The semiconductor structure further includes a resist protection oxide (RPO) layer formed over the pre-determined region, wherein the RPO layer has a level of nitrogen of about 0.35 atomic % or less.

Image sensor having an RPO layer containing nitrogen

A method of stabilizing plating film impurities in an electrochemical plating bath solution is disclosed. The method includes providing an electrochemical plating machine in which an electrochemical plating process is carried out. A by-product bath solution is formed by continually removing a pre-filtered bath solution from the machine and removing an additive from the pre-filtered bath solution. A clean bath solution is formed by removing an additive by-product from the by-product bath solution. An additive bath solution is formed by adding a fresh additive to the clean bath solution. The additive bath solution is added to the electrochemical plating machine. An apparatus for stabilizing film impurities in an electrochemical plating bath solution is also disclosed.

Method and apparatus for stabilizing plating film impurities

A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

Method for preventing voids in metal interconnects

A method of reducing copper hillocks in copper metallization is described. An opening is made through a dielectric layer overlying a substrate on a wafer. A copper layer is formed overlying the dielectric layer and completely filling the opening. The copper layer is polished back to leave the copper layer only within the opening. Copper hillocks are reduced by applying F ions to the copper layer to form a buffer zone on a surface of the copper layer and in-situ depositing a capping layer overlying the copper layer. The F ions remove copper oxide naturally formed on the copper surface and the buffer zone transfers thermal vertical strain in the copper to horizontal strain thereby preventing formation of copper hillocks.

Solution for copper hillock induced by thermal strain with buffer zone for strain relaxation

Within a method for fabricating a microelectronic fabrication there is first provided a substrate having formed thereover a minimum of one microelectronic layer, where the minimum of one microelectronic layer is at least partially transparent to an incident radiation beam. There is then chemical mechanical polish (CMP) planarized the minimum of one microelectronic layer, while employing a chemical mechanical polish (CMP) planarizing method, to form from the minimum of one microelectronic layer a minimum of one chemical mechanical polish (CMP) planarized microelectronic layer. Within the method, a chemical mechanical polish (CMP) planarizing endpoint within the chemical mechanical polish (CMP) planarizing method with respect to the minimum of one chemical mechanical polish (CMP) planarized microelectronic layer is determined while employing the incident radiation beam incident upon the minimum of one microelectronic layer, in conjunction with a derivative of a property of a minimum of one reflected portion of the incident radiation beam reflected from the minimum of one microelectronic layer as the minimum of one microelectronic layer is chemical mechanical polish (CMP) planarized to form the minimum of one chemical mechanical polish (CMP) planarized microelectronic layer.

Chemical mechanical polish (CMP) planarizing method employing derivative signal end-point monitoring and control

A method is provided to prevent the forming of a high de-focusing ledge or step on the back side of a substrate or a semiconductor wafer in order to improve the photolithographic process steps in semiconductor manufacturing. In semiconductor manufacturing, various processes are performed to form various dielectric and metal layers on the front side of wafers. However, some of these materials deposit on the back side of the wafer as well. These unwanted deposits result in contaminants that break off from the back side, causing reliability problems. Those that do stay on, on the other hand, cause irregular topology, thus affecting the focusing of stepper equipment during photolithographic processes. It is disclosed in the present invention a method of forming an oxide layer which prevents the forming of such de-focusing steps on the back side of a wafer.

Prevent defocus issue on wafer with tungsten coating on back-side

A method for monitoring bubble formation in and over a spin-on glass(SOG) layer during the CVD deposition of a superjacent insulative layer is described wherein a monitor wafer is processed either with or without a metal pattern. After a SOG layer has been deposited and cured, a layer of silicon oxide is deposited over it by CVD. If bubbles are formed during the silicon oxide deposition step as a result of out-gassing of the SOG layer, they are entrapped at or near the SOG/silicon oxide interface. The silicon oxide layer is then subjected to a buffered HF etch which exposes the bubbles either by opening them up by eroding the SOG layer underneath the oxide layer or by bringing the surface of the silicon oxide layer closer to the entrapped bubbles, thereby decorating them to make them visible to a white light scanning tool. The monitor wafer is initially scanned just prior to the SOG deposition to obtain a reference scan. A final scan is made after the deposited surface oxide layer has received the buffered HF etch. Bubbles formed over and in an improperly cured SOG layer, occur in clusters that reveal a swirling pattern, reflecting the spin deposition step. The monitor and method of use provides a convenient means for detecting problems with the SOG deposition and curing process, thereby permitting timely remedial action to re-center a deviate process.

Method for monitoring bubble formation and abnormal via defects in a spin-on-glass planarization, etchback process

The present invention relates to the fabrication of semiconductor devices and more particularly to a new method for avoiding abnormal via holes when Spin On Glass, SOG, is used as a means of planarizing an interlevel metal interconnect structure. The invention addresses the problem of locations of micro bubbles in a SOG layer that can lead to seams, voids and a ragged surface topology which, in turn, can make it very difficult to eventually etch well formed via holes at such locations. The invention details a new etch back method that solves the above problem by properly smoothing the micro bubble locations. This new method includes a sequence of anisotropic and isotropic etching steps that are used to partially etch back the cured SOG layer in order to achieve a planarized surface while also smoothing the micro bubble locations in the cured SOG layer. By having first smoothed out the micro bubble locations, it is then possible to deposit an overlying conventional CVD oxide layer without creating highly detrimental seams and voids above the original micro bubble locations. By greatly minimizing such seams and voids, and their associated tendency for uncontrollable etching behavior, proper etching of via holes is now achievable above the original micro bubble locations and the above problem of abnormal via holes is solved.

Etch back method for smoothing microbubble-generated defects in

A flash EPROM device includes a floating gate electrode with a top surface and sidewalls is formed on a gate oxide layer covering a semiconductor substrate. A polyoxide cap layer is formed on the top surface of the floating gate electrode. A blanket tunnel oxide layer covers the cap layer, the sidewalls of the floating gate electrode, and the exposed surfaces of the gate oxide layer. A spacer structure is formed on the surface of the tunnel oxide layer adjacent to the sidewalls of the floating gate electrode and above the gate oxide layer. A dielectric, silicon nitride inner spacer, having an annular or an L-shaped cross section, is formed on the blanket tunnel oxide layer adjacent to the sidewalls of the floating gate electrode. In the case of the L-shaped cross section inner spacer, an outer dielectric, spacer is formed over the inner dielectric, spacer. A blanket interelectrode dielectric layer covers the blanket tunnel oxide layer, and the spacer structure. A control gate electrode is formed over the interelectrode dielectric layer on one side of the floating gate electrode.

Nitride spacer technology for flash EPROM

A method is provided for forming nitride spacers for flash EEPROM devices. A silicon nitride layer is formed over the floating gate in a memory cell. Unlike in conventional methods where the nitride layer is usually subjected to anisotropic etching, it is disclosed in this invention that when partial isotropic/anisotropic etching of a particular recipe is performed, the resulting nitride spacers are better controlled dimensionally with the attendant advantage, therefore, of better definition of gate and channel lengths during subsequent implantations. In a second embodiment, the partial isotropic/anisotropic etching is followed by full anisotropic etching of another recipe with even better defined parameters for the flash EEPROMS.

Method of forming flash EPROM by using iso+aniso silicon nitride spacer

A method for etching access opening to aluminum alloy wire bonding pads of integrated circuit chips is described wherein a polymer layer is in-situ deposited into the opening after the bonding pad has been exposed by dry etching of a passivation layer. The passivation layer, is first etched with fluorocarbon etchants and then a TiN ARC layer is removed from over the aluminum bonding pad with etchants which may contain chlorine either as etch components or as a contaminant in an etchant such as SF.sub.6 non-volatile chlorine containing residues including AlCl.sub.3 and trapped Cl.sub.2, are left behind after the ARC layer has been removed. These cause corrosion of the bonding pad when exposed to atmospheric moisture. The polymer layer deposited immediately after the pad surface is exposed by the etchant, provides a temporary seal over the aluminum bonding pad, protecting it from exposure to moisture during subsequent processing steps.

Process for preventing corrosion of aluminum bonding pads after

A method of forming a spacer structure adjacent to the sidewall of a floating gate electrode with a top surface and sidewalls, the floating gate electrode being formed on a silicon oxide dielectric layer, and the silicon oxide dielectric layer being formed on the top surface of a semiconductor substrate include the following steps. Form a cap layer on the floating gate electrode, and a blanket tunnel oxide on the device. Form an inner dielectric, spacer layer over the device including the cap layer and the sidewalls thereby with conforming sidewalls, and an outer dielectric, spacer layer over the inner dielectric, spacer layer including the conforming sidewalls. Partially etch away the outer dielectric, spacer layer with a dry etch to form a outer dielectric spacer adjacent to the conforming sidewalls. Then partially etch away more of the outer dielectric, spacer layer with a wet etch to expose a portion of the conforming sidewalls of the inner dielectric, spacer layer. Finally, etch away the portion of the inner dielectric, spacer layer unprotected by the outer dielectric spacer before forming interelectrode dielectric layers and the control gate electrode.

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Sinfong, Taiwan

Chen-Peng Fan