Taiwan Semiconductor Manufacturing Comp. Ltd.

Taiwan Semincodcutor Manufacturing Company, Ltd.

Chen-Ming Lee

Mei-Yun Wang

Fu-Kai Yang

I-Wen Wu

Chun-Han Chen

Po-Yu Huang

Shao-Ming Koh

Wei-Yang Lee

Jr-Hung Li

Jia-Heng Wang

Chien-Yuan Chen

Yun Lee

Chung-Ting Ko

Bo-Cyuan Lu

Jui-Ping Lin

Chen-Hung Tsai

Kai-Di Tzeng

Kuo-Yi Chao

Peng Wang

Kai-Hsuan Lee

Chao-Hsun Wang

Shih-Che Lin

Ting Fang

Wei-Yuan Lu

Kuo-Ju Chen

Sheng-Hsiung Wang

Guan-Ren Wang

Pei-Yu Chou

Chun-An Lin

Yi-Jyun Huang

Chia-Hsien Yao

Chung-Hao Cai

Ruei-Ping Lin

Chi On Chui

Yen-Ming Chen

Chang-Yun Chang

Wei-Jung Lin

Ching-Feng Fu

Tzu-Hsiang Hsu

Yan-Ming Tsai

Hung-Chang Hsu

Liang-Yi Chen

Chun-Wen Nieh

Shih-Chieh Wu

Chun Po Chang

Feng-Cheng Yang

Da-Wen Lin

Jian-Hao Chen

Hsien-Cheng Wang

Tzu-Yang Ho

Yen-Jun Huang

Chun-Po Chang

A semiconductor device includes an active region that extends in a first horizontal direction. A source/drain component is disposed over the active region. A source/drain contact is disposed over the source/drain component. A gate structure is disposed over the active region. The gate structure extends in a second horizontal direction different from the first horizontal direction. Side surfaces of the source/drain contact are substantially more tapered in the second horizontal direction than in the first horizontal direction.

Contact profile optimization for IC device performance improvement

A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer.

Silicide backside contact

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece including a semiconductor fin protruding from a substrate, a first placeholder gate and a second placeholder gate over channel regions of the semiconductor fin, and a source/drain feature disposed between the channel regions. The method also includes removing a portion of the first placeholder gate and a portion of the substrate directly disposed thereunder to form an isolation trench, forming a dielectric feature in the isolation trench, replacing the second placeholder gate with a metal gate stack, selectively recessing the dielectric feature, forming a first capping layer over the metal gate stack and a second capping layer over the recessed dielectric feature, and forming a source/drain contact over and electrically coupled to the source/drain feature.

Isolation structure and a self-aligned capping layer formed thereon

A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Semiconductor device structure and method for forming the same

In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.

Semiconductor devices

A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure, and an S/D contact structure formed adjacent to the gate structure. The FinFET device structure includes a protection layer formed on the S/D contact structure, and an S/D conductive plug formed over the protection layer. The S/D conductive plug is electrically connected to the S/D contact structure by the protection layer.

Fin field effect transistor (FinFET) device structure with protection layer and method for forming the same

Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Epitaxial source/drain structures for multigate devices and methods of fabricating thereof

An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Dielectric structures for semiconductor device structures

A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Methods of forming air spacers in semiconductor devices

A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes receiving a workpiece including a fin structure over a front side of a substrate, recessing a source region of the fin structure to form a source opening, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a first wet etching process to remove a portion of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate, performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening, depositing a dielectric layer in the dielectric opening, and replacing the semiconductor plug with a backside source contact.

Method of forming backside power rails

A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

Silicide structures in transistors and methods of forming

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.

Semiconductor device structure and methods of forming the same

A method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (CESL) over the source/drain region, depositing an inter-layer dielectric over the CESL, etching the inter-layer dielectric and the CESL to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. The method further includes depositing a metal layer extending into the contact opening. Horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. An annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. The contact opening is filled to form a source/drain contact plug.

Gate-all-around transistor with reduced source/drain contact resistance

A semiconductor structure includes an active region including a source/drain feature, a contact protruding from a bottom surface of the source/drain feature, a first dielectric layer disposed directly below the active region and surrounding the contact, an air gap disposed between the contact and the first dielectric layer, and a seal disposed between the contact and the first dielectric layer, such that the air gap is disposed between the seal and the source/drain feature.

Backside contact with air spacer

In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

Semiconductor device and method

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Taoyuan County, Taiwan

Chen-Ming Lee