Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Chen-Ming Huang

Chih-Jen Wu

An-Chun Tu

Wen-An Liang

Hung-Cheng Sung

I-Ming Tseng

Kuan-Chieh Huang

Dun-Nian Yaung

Chia-Ta Hsieh

You-Hua Chou

Chih-Tsung Lee

Ching-Ling Lin

Josh Lin

Chi-Wei Ho

Min Hao Hong

Der-Shin Shyu

Ya-Chen Kao

Chin-Hsiang Lin

Chi-Hsin Lo

Rai-Min Huang

Chang-Jen Hsieh

Kuan-Hsien Li

Chia-Shiung Tsai

Wen-Ting Chu

Chung-Yi Yu

Shiu-Ko JangJian

Po-Wei Liu

Wen-Tuo Huang

Hung-Ling Shih

Shih-Chi Lin

Yu-Ling Hsu

Yi-Wen Chen

Shih-Hsien Chen

Chun-Tsen Lu

Tong-Jyun Huang

Chia-Sheng Lin

Miao-Cheng Liao

Yu-Chun Chang

Soon-Kang Huang

Chih-Yuan Yang

Wei-Lin Chang

Kun-Tai Wu

ShihKuang Yang

Yu-Hsiang Yang

Chin-Hsiang Chang

Shih-Chang Liu

Yu-Ping Wang

Po-Kai Hsu

Chien-Ming Lai

Kun-Ju Li

Ya-Huei Tsai

Shih-Jung Tu

Han-Ping Chen

Nai-Chao Su

Hsiang-Hsiang Ko

Lu-Sheng Chou

Yu-Tung Hsiao

Kao-Chao Lin

Sen-Shan Yang

Ching-Hsiang Chiu

Li-Wen Chang

Shih-Ching Lee

Yeur-Luen Tu

Li-Wei Feng

Shih-Hung Tsai

Shih-Fang Tzou

Jyh-Shyang Jenq

Chi-Yuan Shih

Feng-Jia Shiu

Yi-Shin Chu

Chao-Hung Lin

Shui-Yen Lu

Jen-Sheng Yang

Chun-Heng Chen

Hung-Jen Lin

Po-Cheng Huang

Chih-Hong Hwang

Hsiang Hsiang Ko

Yi Hsien Lu

Shih Wei Wang

Min-Hao Hong

Ren-Peng Huang

Ching-Fu Lin

Derek Lin

Jian-Wei Chen

Hsiu Ouyang

Chih-Jung Su

Chen-Chien Li

Kuei-Shu Chang-Liao

Ming-Huei Lien

Hsui Ouyang

Li-Chuen Cheng

Chih-Chen Ku

San-Sun Yang

A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Semiconductor device and method for fabricating the same

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a first conductive structure over a substrate. A first intermediate sidewall spacer is formed to surround the first conductive structure. A masking material is formed over the substrate and around the first intermediate sidewall spacer. A part of the first intermediate sidewall spacer protrudes outward from the masking material. The part of the first intermediate sidewall spacer that protrudes outward from the masking material is etched to form a first sidewall spacer.

Semiconductor device and method of manufacturing

A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

ONON sidewall structure for memory device and method for making the same

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate structure over a substrate and laterally surrounded by a first sidewall spacer. The first gate structure protrudes outward from a top of the first sidewall spacer. A second gate structure is over the substrate and is laterally surrounded by a second sidewall spacer. The first gate structure has a first height that is larger than a second height of the second gate structure. The first sidewall spacer has a first cross-sectional profile that is a different shape and a different size than a second cross-sectional profile of the second sidewall spacer.

ONON sidewall structure for memory device and methods of making the same

A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.

Method of using a polishing system

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip having a flash gate structure disposed over a substrate and including a control gate separated from a floating gate by an inter-electrode dielectric. One or more first sidewall spacers laterally surround the flash gate structure. The inter-electrode dielectric is directly between the one or more first sidewall spacers. A logic gate structure is disposed over the substrate and is laterally surrounded by one or more second sidewall spacers having a smaller height than the one or more first sidewall spacers.

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate disposed over a substrate and having a first height measured between an upper surface of the substrate and a first uppermost surface of the first gate structure. A second gate structure is disposed over the substrate and has a second height measured between the upper surface of the substrate and a second uppermost surface of the second gate structure. The second height is smaller than the first height. A first sidewall spacer laterally surrounds the first gate structure and is recessed below the first uppermost surface. A second sidewall spacer laterally surrounds the second gate structure. A top of the first sidewall spacer is arranged along a horizontal plane that is vertically between the first uppermost surface and the second uppermost surface.

A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.

Polishing system

A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.

Method for fabricating semiconductor device

A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.

Semiconductor device with metal gate

Growing community of inventors

Hsinchu, Taiwan

Chen-Ming Huang