Au Optronics Corporation

Industrial Technology Research Institute

Chunghwa Picture Tubes, Ltd.

Chen-Ming Chen

Yu-Hsin Ting

Da-Wei Fan

Sheng-Chao Liu

I-Fang Chen

Szu-Chieh Chen

Yi-Xuan Hung

Jiun-Jye Chang

Yung-Fu Wu

Kuang-Hsiang Liu

Fang-Tsun Chu

Chun-Yao Huang

Yu-Wu Wang

Cheng-Chung Chen

Chung-Lin Fu

Ling-Ying Chien

Huai-Yuan Tseng

Wann-Hsin Chen

Ming-Tien Lin

I-Hsuan Hung

Yung-chan Chou

A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a second scan line, a data line, a first thin-film transistor, a second thin-film transistor, a first pixel electrode and a second pixel electrode. The first thin-film transistor is electrically connected to the first scan line and the data line. The first pixel electrode is electrically connected to the first thin-film transistor. The second thin-film transistor is electrically connected to the second scan line and the data line. The second pixel electrode is electrically connected to the second thin-film transistor. The orthogonal projection pattern of the first thin-film transistor on XY plane and the orthogonal projection pattern of the second thin-film transistor on XY plane are substantially the same.

Pixel array and display panel

A display includes a plurality of pixels, a plurality of scan lines and a plurality of data lines. Each pixel includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. The scan lines and the data lines are coupled to the pixels. Two color sub-pixels in the same row coupled to the same data line are coupled to different scan lines, and all of the second color sub-pixels in the same row are coupled to the same scan line.

Display and method of generating an image with uniform brightness

An Nshift register unit includes an input circuit, a voltage regulator, and an output circuit. The input circuit is disposed to control a voltage at a control node of the Nshift register unit according to a first scan signal of an (N&#x2212;K)shift register unit or a second scan signal of an (N+K)shift register unit. The voltage regulator includes a first coupling element coupled to a first clock, a first switch disposed to receive the voltage at the control node and generate a reverse bias for reducing current leakage, and a switch control unit disposed to control the first switch according to the first clock. The output circuit is disposed to output a third scan signal.

Shift register circuit and driving method thereof

A display panel includes a plurality of first driving switches installed at a first side of the display panel, a plurality of second switches installed at a second side of the display panel, a plurality of first data lines, a plurality of second data lines, a plurality of scan lines, and a plurality of pixels. Each of the first driving switches includes a first input end and a plurality of first output ends. Each of the second driving switches includes a second input end and a plurality of second output ends. The first data lines are electrically connected to the first output ends. The second data lines are electrically connected to the second output ends. The plurality of pixels are electrically connected to the plurality of first data lines, second data lines and scan lines for displaying images. The first data lines and the second data lines are arranged interlacedly.

Display panel having a plurality of multiplexers for driving a plurality of first driving switches and a plurality of second driving switches

A discharging device is used to reduce the voltage level at a bootstrap point in an electronic circuit such as a shift register circuit. In such a circuit, a first transistor in a conducting state receives an input pulse and conveys it to the gate terminal of a second transistor, causing the second transistor to be in a conducting state. This gate terminal is known as a bootstrap point. After receiving the input pulse, an output pulse is produced at one drain/source terminal of the second transistor. During the time period of the output pulse, the first transistor is in a non-conducting state and the voltage level at the bootstrap point is high, imposing a stress upon the first transistor. A discharging circuit consisting of at least one transistor is coupled to the bootstrap point in order to reduce the voltage level at the output pulse period.

Method and device for reducing voltage stress at bootstrap point in electronic circuits

A liquid crystal display device includes a gate driver for generating a first scan signal voltage and a second scan signal voltage, a source driver for generating a first polarity data voltage and a second polarity data voltage, and a liquid crystal display panel having a first pixel set and a second pixel set. Each first and second pixel set includes a first pixel and a second pixel. Both the first pixel of the first pixel set and the second pixel of the second pixel set display grey level based on the first polarity data voltage in response to the first scan signal voltage. Both the second pixel of the first pixel set and the first pixel of the second pixel set display grey level based on the second polarity data voltage in response to the second scan signal voltage.

Data multiplexer architecture for realizing dot inversion mode for use in a liquid crystal display device and associated driving method

Polynucleotides associated with differentiation states of stem cells are provided. Also provided are methods and kits for detecting, identifying and/or discriminating differentiated stem cells from undifferentiated ones by measuring an expression level of one or more genes, such as CBARA1 and LHX 6, in the stem cells.

CBARA1 and LHX6 cell markers for embryonic stem cells

A bidirectional controlling device is utilized for receiving two input signals, which are respectively provided from a first input terminal and a second input terminal, and for respectively providing two output signals to a first output terminal and a second output terminal, by controlling a plurality of switch sets.

Bidirectional controlling device for increasing resistance of elements on voltage stress

A thin film transistor array, an electrostatic discharge protective device thereof, and methods for fabricating the same are provided. The thin film transistor array comprises a plurality of scan lines, a plurality of data lines, a first shorting bar, and a second shorting bar. The electrostatic discharge protective device comprises a switching device and a resistance line in parallel. If static electricity accumulated on the TFT array is over a predetermined range, the accumulated static electricity will be conducted to the first or second shorting bar via the switching device. The resistance line can prevent signals applied to one of the scan lines or data lines from being conducted to other scan lines or data lines, to detect a defective pixel.

Thin film transistor array and electrostatic discharge protective device thereof

The present invention relates to a method of manufacturing an AMOLED panel. The method comprises providing a substrate, forming a data line and a drain metal on the substrate, forming a buffer insulator layer, forming an active layer, forming a gate insulator layer, forming a gate metal, performing an ion doping to form a source and a drain, forming a via hole, forming a transparent electrode and a pixel define layer, and forming a LED on the transparent electrode.

Method of manufacturing an AMOLED

The present invention relating to a method of manufacturing an AMOLED panel. The method comprises providing a substrate, forming a TFT on the substrate, forming an inter-layer insulator layer, forming a plurality of via holes, forming a metal layer which electrically contacts a source and a drain, forming a transparent electrode, a pixel define layer and a LED. Because the present invention omits a passivation layer, the cost decreases and the process is simpler.

A silicon layer is formed on a substrate, and then the silicon layer is patterned, and source regions, drain regions and connectors, all with the same conductivity, are formed. The source regions are connected with the drain regions electrically by the connectors, and short circuits are thus constructed. Then, subsequent procedures of thin film transistor fabrication are performed in turn. Finally, when the source/drain metal is patterned to form data lines, the connectors are cut off by etching as the source/drain metal is etched.

Method of forming thin-film transistor devices with electro-static discharge protection

A thin film transistor and a method for fabricating the same. The thin film transistor comprises a substrate and a patterned semiconductive layer formed on the substrate, wherein the semiconductive layer comprises a channel region and doped regions adjacent to the channel region. A gate insulating layer is formed on the above structure. A gate electrode is located on the gate insulating layer above the channel region. Source and drain electrodes are located on the gate insulating layer adjacent to the semiconductive layer. A dielectric layer having contact holes is formed on the above structure and a patterned conductive layer is formed on predetermined parts of the dielectric layer electrically connecting the doped regions to the source and drain electrode through the contact holes.

Growing community of inventors

Taichung, Taiwan

Chen-Ming Chen