Winbond Electronics Corporation

Chen-Lung Huang

Ping-Kun Wang

Shao-Ching Liao

Chien-Min Wu

He-Hsuan Chao

Chi-Ching Liu

A resistive memory including a first storage circuit, a verification circuit, a second storage circuit and a control circuit is provided. The first storage circuit includes various cell groups. Each of the cell groups includes at least one memory cell. The verification circuit is coupled to the first storage circuit to verify whether a specific operation performed on at least one of the memory cells was successful. The second storage circuit includes various flag bits. Each of the flag bits corresponds to a cell group. In a reset period, the control circuit is configured to perform a first reset operation or a second reset operation on a first memory cell of a specific cell group among the cell groups according to a specific flag bit corresponding to the specific cell group.

Growing community of inventors

Taipei, Taiwan

Chen-Lung Huang