Au Optronics Corporation

Chen-Lun Chiu

Shih-Hsun Lo

Chien-Liang Chen

Yi-Suei Liao

Hao-Chieh Lee

Hsiang-Yuan Cheng

Shan-Fu Yuan

Yu-Wei Liao

Kuan-Yu Chen

Yang-En Wu

Jen-Chieh Chen

Hsiao-Chung Cheng

Chun-Ching Wei

Chun-Hsien Yeh

Chia-Yang Cheng

Chung-Ming Shen

Chien-Feng Chiu

Yen-hsien Yeh

An exemplary display panel includes a plurality of monochrome pixels, a plurality of data lines and a plurality of control lines. Each monochrome pixel provides a specific color on the display panel. The data lines are electrically coupled to the monochrome pixels for providing the display data. The data lines includes a first data line electrically coupled to a part of the monochrome pixels, and the specific colors provided by the part of the monochrome pixels are of the same color. Besides, each of the control lines is electrically coupled to a part of the monochrome pixels for controlling the part of the monochrome pixels electrically coupled thereto whether to receive the display data from the data lines.

Display panel with improving display quality

Exemplary backlight driving method and display device are provided. The display device includes a light source array. The light source array includes a first group of light-emitting rows and a second group of light-emitting rows. The backlight driving method includes the steps of: firstly, receiving a gate driving frequency of the display device; subsequently, generating a backlight driving frequency according to the gate driving frequency; and afterwards, sequentially providing a first row driving voltage to the first group of light-emitting rows in a first time period and sequentially providing a second row driving voltage to the second group of light-emitting rows in a second time period, according to the backlight driving frequency. The first time period and the second time period have different phases from each other, and the gate driving frequency is different from the backlight driving frequency.

Backlight driving method and display device

A naked-eye type stereoscopic display including a display panel, a polarization switching panel, and a lens array is provided. The display panel provides an image having a first polarization state. The polarization switching panel and the lens array are disposed on a propagation path of the image, and the polarization switching panel is located between the lens array and the display panel. In addition, the polarization switching panel has at least one rescue line so as to lower the scrap rate of the polarization switching panel.

Naked-eye type stereoscopic display

A flat panel display, a shift register with image retention release and method for releasing image retention are provided. An output end of the shift register couples to a gate line of a display panel. A first end of a first transistor couples to the output end of the shift register. A second end of the first transistor couples to a system voltage VDD or a reference voltage VSS. A first end of a capacitor couples to a control end of the first transistor. A second end of the capacitor couples to the reference voltage VSS. During a power-off period, the reference voltage VSS is pulled high for turning on the first transistor, therefore the voltage of the gate line is pulled high.

Shift register with image retention release and method for image retention release

A shift register apparatus is provided. The pull-down unit of each of the shift registers in the shift register apparatus is controlled by itself, previous, and next two shift registers to enhance the ability of pull-down and voltage regulating. Therefore, the circuit structure of each of the shift registers does not need to be designed a large compensation capacitor therein to substantially restrain the coupling noise effect caused by the clock signal, and thus permitting that each of the shift registers can be collocated with a small compensation capacitor to enhance the output capability thereof.

Shift register apparatus

A shift register having individual driving nodes is disclosed. The shift register includes a first clock pull-down module, a second clock pull-down module, a key pull-down module, a self feedback module, and a driving output unit. The first clock pull-down module is used to pull-down the potential of a gate line to a low voltage when the first clock signal is in a high voltage level. The second clock signal pull-down module pulls down the potential of the gate line to the low voltage when the second clock signal is in a high voltage level. The key pull-down module rapidly pulls down the potential of the gate line to the low voltage level after the gate line outputs an output signal. The self feedback module is used to output a driving signal to the key pull-down module. The driving signal output unit outputs a next stage driving signal which is irrelative to the operation of the previous stage shift register.

Shift register with individual driving node

Growing community of inventors

Hsin-Chu, Taiwan

Chen-Lun Chiu