Holtek Semiconductor Corp.

Holtek Microelectronics Inc.

Chen Ling

Siu-han Liao

A new structure of a triple-well non-volatile semiconductor memory cell array and a method of fabricating the memory arrays are described. The circuit layout of the memory array not only includes the conventional floating gates, control gates, cell sources and cell drains, but also adds the local source regions to increase the coupling ratio. Besides, the new design can reduce the number of contact windows, further increasing the packing density of the memory array. The key point of the method is the triple-well formation inside the silicon substrate that lowers the operational voltage of periphery circuit. Furthermore, there are two additional isolation regions between two adjacent metal lines, which can minimize the possibility of cross talk due to shirking spacing.

Low-voltage triple-well non-volatile semiconductor memory

A new structure of a non-volatile semiconductor memory cell array and a method of fabricating the memory arrays. The circuit layout of the memory array not only comprises of the conventional floating gates, control gates, cell sources and cell drains, but also adds the local source regions to increase the coupling ratio. Besides, the new design can reduce the number of metal contact windows, further increase the packing density of the memory array. Furthermore, an additional isolation region is formed between two bit lines so as to increase the distance between two bit lines, which can minimize the possibility of cross talk due to shirking spacing.

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Sunnyvale, CA, United States of America

Chen Ling