Csmc Technologies Fab2 Co., Ltd.

Len Technology Limited

Chen Li

Hao Wang

Jingquan Chen

An analog-to-digital converter and a thermopile array. The analog-to-digital converter comprises: a reference voltage generation circuit comprising a voltage generation unit; a chopping modulation unit used to perform chopping modulation on a voltage signal generated by the voltage generation unit, and to modulate low frequency noise of the voltage signal into high frequency noise; and a low-pass filter used to eliminate the high frequency noise to obtain a reference voltage. The invention employs a simple structure to obtain a low noise reference voltage at low costs.

Analog-to-digital converter and thermopile array

The present application provides an LED control system, including an LED driver chip, a thermistor independent of the LED driver chip, and a matching resistor of the thermistor, wherein different thermistors correspond to different matching resistors; the LED driver chip and the matching resistor are configured to generate corresponding LED control targets according to different thermistors; wherein the upper and lower limits of the control targets are preset by the LED driver chip regardless of the thermistor; and the slope of the change of control target over the change of temperature is fitted with the slope of the change of thermistor resistance over the change of temperature, and the upper and lower limits of the control target remains the same for different choices of thermistors. The present application also provides a corresponding LED control method.

LED control method and system

An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal.

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Wuxi, China

Chen Li