Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Jung Wang

Sin-Yi Yang

Han-Ting Lin

Tai-Yen Peng

Yu-Shu Chen

Jyu-Horng Shieh

Qiang Fu

Chien Chung Huang

Chih-Yuan Ting

Hui-Hsien Wei

Chien-Chung Huang

Huan-Just Lin

An-Shen Chang

Jiann-Horng Lin

Kun-Yi Li

Hua-Tai Lin

Chang-Sheng Lin

Yu-Feng Yin

Han-Wei Wu

Yuan-Hsiang Lung

Wei-De Ho

Pei-Sheng Tang

Yin-Hao Wu

Hsing-Hsiang Wang

Meng-Chieh Wen

Lin-Ting Lin

An integrated circuit includes a metallization pattern having first and second conductive features, an etch stop layer over the metallization pattern, a memory device, a bottom electrode via, a third conductive feature, and a dielectric feature. The etch stop layer has first and second portions over the first and second conductive features, respectively. The bottom electrode via is in the first portion of the etch stop layer and electrically connecting the memory device over the first portion of the etch stop layer to the first conductive feature. The third conductive feature is in the second portion of the etch stop layer and electrically connected to the second conductive feature. The dielectric feature is between the first and second portions of the etch stop layer and in contact with sidewalls of the first and second portions of the etch stop layer.

Integrated circuit

A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Gradient protection layer in MTJ manufacturing

A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalls of the pillar structures.

Semiconductor structure and method for forming the same

In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

Magnetic tunnel junction device

The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.

Semiconductor structure and manufacturing method of the same

An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.

A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalk of the pillar structures.

In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

Etch monitoring and performing

The present disclosure provides a method for manufacturing semiconductor structure, including forming an insulation layer, forming a first via trench in the insulation layer, forming a barrier layer in the first via trench, forming a bottom electrode via in the first via trench, forming a magnetic tunneling junction (MTJ) layer above the bottom electrode via, and performing an ion beam etching operation, including patterning the MTJ layer to form an MTJ and removing a portion of the insulation layer from a top surface.

A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.

Metal etching stop layer in magnetic tunnel junction memory cells

A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.

Memory device structure and method for forming the same

Magnetic of forming magnetic tunnel junction device using protective mask

An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.

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Hsinchu, Taiwan

Chen-Jung Wang