Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Hui Hsieh

Chung-Cheng Chou

Hank Cheng

Hau-Tai Shieh

Kun Lung Chen

Wei-Chia Cheng

Chien-Hua Huang

Shine Chung

Chi-Ting Cheng

Tao-Ping Wang

Chingwen Chang

Shih-Chieh Lin

Grigori Grigoriev

An integrated circuit structure includes one or more external contact pads with decoupling capacitors, such as metal-insulator-metal (MIM) capacitors, formed directly thereunder. In an embodiment, the decoupling capacitors are formed below the first metallization layer, and in another embodiment, the decoupling capacitors are formed in the uppermost inter-metal dielectric layer. A bottom plate of the decoupling capacitors is electrically coupled to one of Vand V, and the top plate of the decoupling capacitors is electrically coupled to the other. The decoupling capacitors may include an array of decoupling capacitors formed under the external contact pads and may include one or more dummy decoupling capacitors. The one or more dummy decoupling capacitors are MIM capacitors in which at least one of the top plate and the bottom plate is not electrically coupled to an external contact pad.

MIM decoupling capacitors under a contact pad

A bias voltage monitoring circuit is disclosed which comprises a first device coupled between a positive high voltage power supply (VDD) and a first node, a second device coupled between the first node and a second node where the bias voltage is applied, and a pad coupled to the first node, wherein the first and second devices form a voltage divider and a voltage measured at the pad reflects the bias voltage, and the first device and the second device is so chosen that a voltage at the first node is always positive for a given range of the bias voltage.

System and method for monitoring negative bias in integrated circuits

A low-voltage sub-bandgap reference circuit is disclosed. In one embodiment, the low-voltage sub-bandgap voltage reference circuit includes a differential amplifier and a first bipolar transistor with its base and collector coupled to an electrical ground. The reference circuit further includes a second bipolar transistor with base and collector coupled to the electrical ground. The reference circuit further includes a DC bias circuit supplying a predetermined voltage output between a high and low voltage terminal, the high voltage terminal being coupled to both collectors of the first and second bipolar transistors and the low voltage terminal being coupled to both bases of the first and second bipolar transistors.

Ultra low-voltage sub-bandgap voltage reference generator

A method and apparatus are provided for sensing in low voltage DRAM memory cells. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first and second NMOS transistor, each having a source and a first and second PMOS transistor, each having a source. The method further includes the steps of maintaining the voltage of the sources of the first and second NMOS transistors at a first voltage during normal operation and lowering the voltage of the sources of the first and second NMOS transistors from the first voltage to a second voltage during a read operation.

Method for high speed sensing for extra low voltage DRAM

The disclosure generally relates to a method and apparatus for decreasing the frequency of refreshing a memory cell in communication with a word line and a bit line. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first NMOS transistor having a source, a second NMOS transistor having a source, a first PMOS transistor having a source and a second PMOS transistor having a source; maintaining the voltage of the sources of the first and second PMOS transistors at a first voltage during normal operation; and raising the voltage of the sources of the first and second PMOS transistors from the first voltage to a second voltage during a refresh operation.

Method for increasing retention time in DRAM

An integrated circuit device includes an embedded memory having a plurality of memory macros and a built-in-self-test (BIST) circuit coupled to the plurality of memory macros for simultaneous operation of the memory macros, wherein the BIST circuit is configured to select from the memory macros' data outputs an individual memory macro's data output for analysis while the memory macros are operated simultaneously.

Memory with improved BIST

The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line. A method according to one embodiment includes: equalizing the bit line and the complementary bit line to a common voltage; addressing the memory cell by connecting the memory cell to one of the bit line or the complementary bit line; reading the memory cell by detecting a first charge stored in the memory cell and communicated said first charge to one of the bit line or the complementary bit line; and writing a second charge into the memory cell by communicating the second charge to the memory cell through an inverter and one of the bit line or the complementary bit line. In one embodiment, the inverter is activated only to communicate the second charge to the memory cell.

Method and apparatus for high-efficiency operation of a dynamic random access memory

A bidirectional shift register is disclosed which comprises a first and second flip-flop, a first multiplexer having an output coupled to an input of the first flip-flop, and a second multiplexer having an output coupled to an input of the second flip-flop wherein an output of the first flip-flop is coupled to an input of the second multiplexer, an output of the second flip-flop is coupled to an input of the first multiplexer.

Bidirectional shift register

A system for improving reliability of a memory device includes one or more memory banks, each of which has one or more regular memory cell rows and one or more redundant memory cell rows. At least one built-in-self-test (BIST) unit is coupled to the memory banks for testing the redundant memory cell rows to determine their respective quality standards, and testing the regular memory cell rows to identify the regular memory cell row that fails to pass a predetermined quality standard. At least one built-in-self-repair (BISR) unit is coupled to the BIST unit for replacing the failed regular memory cell row with the redundant memory cell row having a quality standard equal to or higher than the predetermined quality standard. The BIST unit repeatedly tests the regular memory cell rows a number of times, with each time applying a different quality standard.

Method and system for improving reliability of memory device

A method for making a semiconductor device having a fuse window above a substrate is disclosed. The semiconductor device has at least one fuse protection circuit located under the fuse window. The fuse protection circuit includes a fuse having a first end connected to a first voltage and a second end. A first transistor having a drain is connected to the second end of the fuse, a gate for receiving an input signal, and a source is connected to a second voltage. A second transistor having a drain is connected to the second end of the fuse, a gate, and a source is connected to the second voltage. A first diode having an anode and a cathode, the anode of the first diode is connected to the second voltage and the cathode of the first diode is connected to the second end of the fuse. A second diode having an anode and a cathode, the anode of the second diode is connected to the second end of the fuse and the cathode of the second diode is connected to the first voltage. A resistor having a first end is connected to the anode of the second diode, and a second end. An inverter having an input end is connected to the second end of the resistor, and an output end is connected to the gate of the second transistor for providing an output signal.

Method for fabricating a protection circuit located under fuse window

A method and system is presented for measuring a data access time of an embedded macro module in an integrated circuit. A single external test signal is inputted into the embedded macro module for enabling a data input therein and extracting a data output therefrom. A pulse width of the single external test signal is incrementally increased until a latch of the data output is observed. Then, the data access time is obtained, as its substantially equals a time interval of the increased pulse width.

Method and system for timing measurement of embedded macro module

A memory cell for a static random access memory (SRAM) is disclosed that can be programmed to have a one-bit cell or a multi-bit cell (i.e, including two or more latches) according to a desired amount of cell current. For lower current needs, the memory cell can incorporate a single bit-element, while for higher current needs the memory cell can incorporate two or more bit-elements. An exemplary static random access memory device includes a memory cell having one or more bit-elements, such as bistable latches. Access devices, such as pass transistors, are coupled between each of the bit-elements and a bit line. A word line is coupled to the control terminal of each of the pass transistors for controlling communication between the bit-elements and the bit line.

Static random access memory device having a memory cell with multiple bit-elements

A semiconductor device having a fuse window above a substrate, the semiconductor device has at least one fuse protection circuit located under the fuse window. The fuse protection circuit includes a fuse having a first end connected to a first voltage and a second end. A first transistor having a drain is connected to the second end of the fuse, a gate for receiving an input signal, and a source is connected to a second voltage. A second transistor having a drain is connected to the second end of the fuse, a gate, and a source is connected to the second voltage. A first diode having an anode and a cathode, the anode of the first diode is connected to the second voltage and the cathode of the first diode is connected to the second end of the fuse.

Protection circuit located under fuse window

A fuse state detection circuit () has a reference circuit part (') and a fuse detection circuit part (&#x2032;), the reference circuit part (&#x2032;) having a fuse (&#x2032;) identical to a fuse (&#x2032;) under detection. A reference voltage is between a voltage of a blown fuse (&#x2032;) under detection and a voltage of an un-blown fuse (&#x2032;) under detection, thus distinguishing a blown state of the fuse (&#x2032;) under detection from an un-blown state of the fuse (&#x2032;) under detection.

Growing community of inventors

Chu-Pei, Taiwan

Chen-Hui Hsieh