Alcatel-lucent USA Inc.

Lucent Technologies Inc.

Alcatel Lucent

Chen-Huan Chiang

Bradford Van Treuren

Tapan J Chakraborty

Suresh Goyal

Michele Portolan

Kenneth Y Ho

Victor J Velasco

Paul James Wheatley

Ken Cheung

John A Andersen

Robert W Barr

Dante De Rogatis

Bradford Gene Van Treuren

Tapan Jyoti Chakraborty

A distributed test architecture of transmitting boundary scan Test Access Port (TAP_signals over a serial channel is disclosed. The architecture facilitates the system testing and remote field update of distributed base stations in a wireless network. The distributed test architecture enables system testing as if the distributed units are on a backplane within the same chassis by creating a plurality of logical connections between the distributed unit and the test bus using a single bit fiber line and a five bit TAP test bus.

Distributed base station test bus architecture in a wireless network

The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.

Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing

The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level. In one embodiment, when the second hierarchical level is deselected, the control logic prevents data from being propagated within the second hierarchical level while data is propagated within the first hierarchical level. In one embodiment, the second hierarchical level may be used for independent, parallel testing while data continues to be propagated through the first hierarchical level.

Apparatus and method for isolating portions of a scan path of a system-on-chip

The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.

Method and apparatus for describing and testing a system-on-chip

The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.

Apparatus and method for controlling dynamic modification of a scan path

The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.

Method and apparatus for describing parallel access to a system-on-chip

A slow fast programming method for efficient remote field update in distributed base stations overcomes significant fiber propagation delay associated with a remote unit by applying programming data at two clock frequencies. A fast clock frequency is used for programming data phases that do not require a response from the remote unit, and a slow clock frequency is used for programming data phases that require a response from the remote unit. Testing a base unit and a remote unit is also accomplished with more than one clock based on the test dependence on a remote response.

Slow-fast programming of distributed base stations in a wireless network

A method and system are disclosed for fault injection using Boundary Scan resources compliant with 1149.1, while operating in system mode. The system has two register circuits, one, for storing and updating fault selection data and another, for storing and updating fault injection values.

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Princeton Junction, NJ, United States of America

Chen-Huan Chiang