Southeast University

Nanjing Legend Biotech Co., Ltd.

Chen Hu

Jie Li

Na Bai

Longxing Shi

Jun Yang

Shu Wu

Shuai Yang

Chao Wang

Jian Liu

Yuanyuan Peng

Aiguo Bu

Qing Dai

Ming Ling

Kun Jiang

Described herein are T cells engineered to express a chimeric antigen receptor (CAR), such as an anti-mesothelin CAR alone or in combination with a follicle-stimulating hormone receptor (FSHR) binding domain and/or a dominant negative transforming growth factor-β receptor II (dnTGFβRII) for the treatment of diseases associated with mesothelin expression. Also described are T cells engineered to express a modified T cell receptor (TCR).

Anti-mesothelin chimeric antigen receptor (CAR) constructs and uses thereof

A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors Pand Pand five NMOS transistors N&#x2dc;N, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N, N, and Nis connected with the local grid electrode respectively; the base electrode of the NMOS transistors Nand N, are grounded respectively; the NMOS transistor Nform an phase inverter with the PMOS transistor P, and the NMOS transistor Nform another phase inverter with the PMOS transistor P; the two phase inverters are connected with each other in a cross coupling manner via the cut-off NMOS transistor N, the output end of the phase inverter Nand Pdirectly connected to the input end of the phase inverter Nand P, and the output end of the phase inverter Nand Pconnected to the input end of the phase inverter Nand Pvia the cut-off NMOS transistor N; the NMOS transistor Nis connected with the write bit line (WBL) of the phase inverter Nand P, and the NMOS transistor Nis connected with the NOT WBL and read word line (RWL) of the phase inverter Nand P

Sub-threshold memory cell circuit with high density and high robustness

A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.

Capacity and density enhancement circuit for sub-threshold memory unit array

Growing community of inventors

Jiangsu, China

Chen Hu