Freescale Semiconductor,inc.

Nxp Usa, Inc.

Chen He

Richard Eguchi

Fuchen Mu

Yanzhuo Wang

Jon Scott Choy

Daniel Hadad

Katrina M Prosperi

Michael Alan Sadd

Peter J Kuhn

Jon W Weilemann, Ii

Kelly K Taylor

Craig T Swift

Frank Kelsey Baker, Jr

Gary L Miller

Ronald J Syzdek

Benjamin A Schmid

Richard Kenneth Glaeser

Jon W Weilmann, Ii

Nikolas Bradley Sumikawa

Paul A Bogucki

Richard K Eguchi

Frank K Baker Jr

Mu Fuchen

A method and memory for stressing a plurality of non-volatile memory cells is provided. The method includes entering a memory cell stressing mode and providing one or more erase stress pulses to the plurality of non-volatile memory cells; determining that a threshold voltage of at least a subset of the plurality of non-volatile memory cells has a first relationship that is either greater than or less than a first predetermined voltage; providing one or more program stress pulses to the plurality of memory cells; and determining that the threshold voltage of at least a subset of the plurality of memory cells has a second relationship to a second predetermined voltage that is different than the first relationship.

Method and apparatus for stressing a non-volatile memory

A fault analysis method comprises: receiving fault data from wafer level testing that identifies locations and test results of a plurality of die; applying a kernel transform to the fault data to produce cluster data, where the kernel transform defines a fault impact distribution that defines fault contribution from the failed die to local die within an outer radial boundary of the fault impact distribution. Applying the kernel transform comprises: centering the fault impact distribution at a location of each die that failed wafer level testing, associating each local die that falls within the outer radial boundary with a respective fault contribution value according to the fault impact distribution, and accruing fault contribution values associated with each respective die of the plurality of die to produce a cluster value for the respective die, which correlates to a probability of failure of the respective die at a future time.

Kernel based cluster fault analysis

An integrated circuit includes a non-volatile memory module that can censor access to various memory regions based upon a censorship criteria. Information used to implement the censorship criteria is stored at a non-volatile memory location. A one-time programmable non-volatile memory location stores a value representing permanent censorship key. If the permanent censorship key is in an erased state, one or more resources are allowed to modify the non-volatile memory location and disable censorship. If the permanent censorship key has one or more programmed bits, no resource is allowed to modify the non-volatile memory location and disable censorship.

Method for implementing security of non-volatile memory

Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (V) level and an additional embedded erase cycle is performed if any NVM cells are found to exceed the threshold voltage (Vt) check voltage (V) level. The threshold voltage (Vt) check voltage (V) level can be, for example, a voltage level that is slightly higher than an erase verify voltage (V) level and lower than read voltage level (V).

Extended protection for embedded erase of non-volatile memory cells

A method of programming a non-volatile semiconductor memory device includes determining a number of bit cells that failed to program verify during a program operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further determines whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The program operation is considered successful if the number of bit cells that failed to program verify after a predetermined number of program pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.

Programming a non-volatile memory (NVM) system having error correction code (ECC)

A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.

Temperature-based adaptive erase or program parallelism

A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

Adaptive erase methods for non-volatile memory

A method of performing a write operation on memory cells of a memory array includes applying a first plurality of pulses the write operation on the memory cells in accordance with a first predetermined ramp rate, wherein the first plurality of pulses is a predetermined number of pulses; performing a comparison of a threshold voltage of a subset of the memory cells with an interim verify voltage; and if a threshold voltage of any of the subset of memory cells fails the comparison with the interim verify voltage, continuing the write operation by applying a second plurality of pulses on the memory cells in accordance with a second predetermined ramp rate which has an increased ramp rate as compared to the first predetermined ramp rate.

Non-volatile memory (NVM) with adaptive write operations

A non-volatile memory built-in self-trim mechanism is provided by which product reliability can be improved by minimizing drift of reference current used for accessing the non-volatile memory and for performing initial trimming of the reference current. Embodiments perform these tasks by using an analog-to-digital converter to provide a digital representation of the reference current (Iref) and then comparing that digital representation to a stored target range value for Iref and then adjusting a source of Iref accordingly. For a reference current generated by a NVM reference bitcell, program or erase pulses are applied to the reference cell as part of the trimming procedure. For a reference current generated by a bandgap-based circuit, the comparison results can be used to adjust the reference current circuit. In addition, environmental factors, such as temperature, can be used to adjust the measured value for the reference current or the target range value.

Built-in self trim for non-volatile memory reference current

Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.

Adaptive erase recovery for non-volatile memory (NVM) systems

A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation.

Non-volatile memory (NVM) with dynamically adjusted reference current

A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

Test flow to detect a latent leaky bit of a non-volatile memory

A technique for detecting an imminent read failure in a non-volatile memory array includes applying a bulk read stress to a plurality of cells of the non-volatile memory array and determining whether the plurality of cells exhibit an uncorrectable error correcting code (ECC) read during an array integrity check at a margin read verify voltage level subsequent to the bulk read stress. The technique also includes providing an indication of an imminent read failure for the plurality of cells when the plurality of cells exhibit the uncorrectable ECC read during the array integrity check. In this case, the margin read verify voltage level is different from a normal read verify voltage level.

Stress-based techniques for detecting an imminent read failure in a non-volatile memory array

Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric layers for NVM cells that occurs over time from charges (e.g., holes and/or electrons) becoming trapped within these tunnel dielectric layers. NVM operations with respect to which dynamic healing processes can be applied include, for example, erase operations, program operations, and read operations. For example, dynamic healing can be applied where performance for the NVM system degrades beyond a selected performance level for an NVM operation, such as elevated erase/program pulse counts for erase/program operations and bit errors for read operations. A variety of healing techniques can be applied, such as drain stress processes, gate stress processes, and/or other desired healing techniques.

Dynamic healing of non-volatile memory cells

In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.

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Austin, TX, United States of America

Chen He