Wisconsin Alumni Research Foundation

National Science Foundation

Chen-Han Ho

Karthikeyan Sankaralingam

Sung B Kim

Marc Asher De Kruijf

A specialized memory access processor is placed between a main processor and accelerator hardware to handle memory access for the accelerator hardware. The architecture of the memory access processor is designed to allow lower energy memory accesses than can be obtained by the main processor in providing data to the hardware accelerator while providing the hardware accelerator with a sufficiently high bandwidth memory channel. In some embodiments, the main processor may enter a sleep state during accelerator calculations to substantially lower energy consumption.

Computer accelerator system using a trigger architecture memory access processor

A computer architecture allows for simplified recovery after mis-speculation during speculative execution by controlling speculation to occur within idempotent regions that may be recovered by re-execution of the region without the need for restoring complex state information from checkpoints. A compiler for increasing the size of idempotent regions is also disclosed.

Growing community of inventors

Madison, WI, United States of America

Chen-Han Ho