Mellanox Technologies, Ltd.

Mellanox Technologies Tlv Ltd.

Chen Gaist

Ran Ravid

Lavi Koch

Aviv Berg

Dotan David Levi

Liron Mula

Hananel Faig

Thorkild Franck

Ran Sela

Ulrik Wismar

Oren Tzvi Sela

Avner Hadash

Matan Groen

Omer Sella

Afek Bernhard

Liron Mulla

In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.

Synthesized clock synchronization between network devices

In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.

Parallel decision feedback equalizer partitioned for high throughput

Methods and apparatuses are provided for locking a transmitter oscillator to a reference clock signal in a frequency domain. The apparatus includes a digital phase-frequency detector. The digital phase-frequency detector includes a mod-M counter, a mod-N counter, and a count evaluation digital circuit. The mod-M counter is designed to count reference clock cycles of a reference clock signal. The mod-N counter is designed to count local clock cycles of a local clock signal. The count evaluation digital circuit is designed to compare the counted reference clock cycles and the local clock cycles with a predefined register setting to generate a control signal as a feedback signal. The control signal is transmitted to the transmitter oscillator through a frequency-locked loop circuit for adjusting the frequency of the transmitter oscillator to be consistent with the reference clock signal.

Method and apparatus for locking a transmitter oscillator to a reference clock signal in a frequency domain

A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

Synthesized clock synchronization between networks devices

A method for communication includes transmitting a sequence of outgoing data blocks from a network node over a communication link to a peer node, and receiving incoming data blocks from the peer node. A control field is added in a predefined location in each of the outgoing data blocks in the sequence by the network node. In at least a first subset of the outgoing data blocks in the sequence, the control field contains error control information, which is capable of causing the peer node to retransmit one or more of the incoming data blocks to the network node, while in at least a second subset of the outgoing data blocks in the sequence, disjoint from the first subset, the control field contains a flow control instruction, configured to cause the peer node to alter a rate of transmission of the incoming data blocks over the link.

Physical-layer signaling of flow control updates

Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.

Growing community of inventors

Tel Aviv, Israel

Chen Gaist