Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Fu Huang

Lee-Chung Lu

Chung-Hsing Wang

Yi-Kan Cheng

Hsiao-Shu Chao

Ho Che Yu

Chih Sheng Tsai

Shu Yi Ying

Chin-Yu Chiang

An embodiment is a method for providing an adjusted electronic representation of an integrated circuit layout, the method including using one or more processor, generating a timing performance of a path in a first netlist, identifying a first cell in the path that violates a timing performance parameter, and generating a plurality of derivative cells from a subsequent cell that is in the path after the first cell, where each derivative cell includes a variation of the subsequent cell. The method further includes in response to the identifying the first cell, replacing the subsequent cell with at least one of the plurality of derivative cells to generate a first modified netlist, where the variation of the at least one of the plurality of derivative cells reduces the violation of the timing performance parameter, and generating a final netlist based on the first modified netlist.

Optimization for circuit migration

Growing community of inventors

Kaohsiung, Taiwan

Chen-Fu Huang