Tsinghua University

Macronix International Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Fu Chien

Chia-Yu Hsu

Chih-Ping Chen

Shun-Li Lin

Kuo-Hao Chang

Jei-Zheng Wu

Ying-Jen Chen

Chih-Wei Lin

Hong-Hsing Chou

Chih-Wei Hsiao

I-Pien Wu

Shao-Chung Hsu

Chih-Han Hu

Jia-Nian Zheng

Yeh-Jye Wang

Jen-Hsin Wang

Disclosure is a multi-objective semiconductor product capacity planning system and method thereof. The system comprises a data input module, a capacity planning module and a computing module. The machine information of the production stations, the product information and the order information are input by the data input module. According to the demand quantity of order, capacity information and product information, the capacity planning module plans a capacity allocation to determine the satisfied quantity of orders. The capacity allocation information is used to form a gene combination by chromosome encoding method. The computing module calculates the gene combination several times to generate numerous candidate solutions by a multi-objective genetic algorithm. The numerous candidate solutions sorts out and generates a new gene combination, and repeats the calculation to form candidate solution set until stop condition is satisfied. The candidate solution set is transformed into numerous suggestive plans as options.

Multi-objective semiconductor product capacity planning system and method thereof

Disclosure is a method of dispatching semiconductor batch production, including: measuring an actual line width to calculate an estimated value of line width bias reference level, an estimated value of product bias, an estimated value of chamber bias and a standard error of chamber bias, and storing in a historical data module; inputting a product category, a line width measurement before manufacturing and a target line width after manufacturing in a batch production module; calculating a similarity index of each chambers by a computing engine of a matching module according to the data stored in the historical data module; transforming the similarity index into a priority of machine allocation by a dispatching module and dispatching a production machine; updating the historical data module by measuring a line width after manufacturing. The line width bias generated by various variations will be eliminated during the manufacturing process.

Method of dispatching semiconductor batch production

A method for classifying defect images is provided. Defect images are processed through an automatic optical detection. The present invention integrates image analysis and data mining. Defects are found on the images without using human eye. The defects are classified for reducing product defect rate. Thus, the present invention effectively enhances performance on finding and classifying defects with increased consistency, correctness and reliability.

Method of defect image classification through integrating image analysis and data mining

The present invention relates to a photolithography capacity planning system and a non-transitory computer readable media thereof. The photolithography capacity planning system includes a cost calculation module, a capacity calculation module, a demand calculation module, and a data processing module. The cost calculation module calculates a production cost, an unfulfilled demand cost, and a mask cost of the photolithography manufacturing process. The capacity calculation module calculates a capacity of light sources, a capacity of shared equipments, and a capacity of specified equipments of the photolithography manufacturing process. The demand calculation module calculates a quantity of unfulfilled demand. The data processing module produces a planning result.

Photolithography capacity planning system and non-transitory computer readable media thereof

The present invention applies the data mining methodology by which the wafer exposure effectiveness and efficiency are predictable in terms of the chip size, chip length and chip width. More specifically, in the present invention, an index, named 'Mask-field-utilization weighted Overall Wafer Effectiveness' (MOWE), integrates the two parameters of 'Overall Wafer Effectiveness' (OWE) and &#x201c;Mask-Field-Utilization&#x201d; (MFU), mainly regarding the wafer exposure effectiveness and efficiency respectively, in order to construct a model tree of the MOWE to achieve the data mining. By the MOWE model tree, the causal relationship between design independent variables and fabrication dependent variables is constructed, which can be accordingly applied as design guidelines in the design phase to improve the chip layout in order to produce a better wafer exposure effectiveness and efficiency.

Method for enhancing wafer exposure effectiveness and efficiency

A factor analysis system and method thereof is disclosed. The factor analysis system comprises a data receiving module for receiving a plurality of factors having influence on a target total value, a plurality of base values corresponding to the factors, and a target improvement percentage; a first computing unit for computing a reference target total value and a plurality of upgraded target total values; a second computing unit using the upgraded target total values and the reference target total value to compute the sensitivity of each of the factors; and a processing module for multiplying a factor improvement of each factor in percentage point by the factor sensitivity of each factor to obtain the level of contribution of each factor to the target total value. Through the factor analysis, a decision maker can decide the optimal combination of different factor improvements for achieving the planned target total value.

Factor analysis system and analysis method thereof

A method for analyzing overlay errors in lithography is described. Interfield sampling and intrafield sampling are first conducted to sample multiple positions on each of the wafers, and then the overlay error value at each of the positions is measured. An overlay error model including coefficients of intrafield and interfield overlay errors of different types is used to fit the measured overlay error values with respect to the sampled positions. In the overlay error model, the intrafield overlay errors include intrafield translation, isotropic magnification, reticle rotation, asymmetric magnification and asymmetric rotation, and the interfield overlay errors include interfield translation, scale error, wafer rotation and orthogonality error.

Method for analyzing overlay errors

A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted between at least one arranged field and the alignment mark and inserted adjacent to the wafer edge. The total number of dies manufacturable on the wafer at the first position is determined. The wafer position is shifted to a second position relative to the position of the plurality of fields, and the total number of dies manufacturable on the wafer at the second position is determined. The total number of manufacturable dies from each of the first and the second positions is compared, and the positions having the higher number of manufacturable die are candidates of optimal die placement position. Then the total number of fields, the total number of dummies, and the total number of shared dummies are evaluated to decide the optimal die placement position.

Methods for optimizing die placement

In the manufacturing of VLSI circuits, production of overlay is a critical step. To obtain a higher resolution and alignment accuracy in microlithographic process, overlay errors must be measured so that overlay errors can be reduced to a tolerable level. This invention provides an overlay error model and a sampling strategy. Utilizing the overlay model and sampling strategy, a device for measuring overlay errors is also designed.

Overlay error model, sampling strategy and associated equipment for implementation

Conventionally, efforts to improve the yield of chips produced on a wafer focused on defect reduction. Another approach is optimizing wafer exposure patterns. The present invention includes a computer-based procedure and apparatus to expose cells on the surface of a wafer so as to maximize the number of dies produced from a wafer. The invention is useful in the exposure of six and eight inch wafers, as well as larger wafers.

Growing community of inventors

Hsinchu, Taiwan

Chen-Fu Chien