Mediatek Corporation

Chen-Feng Chiang

Ming-Shi Liou

Che-Yuan Jao

Kai-Hsin Chen

Chih-Tsung Yao

An-Siou Li

An I/O driving circuit comprising a post driver. The post driver comprises: a first switch device, comprising a first terminal coupled to an I/O voltage, and comprising a second terminal, wherein the first switch device provides an initial driving voltage at the second terminal of the first switch device; and a first voltage providing device, comprising a first terminal coupled to the second terminal of the first switch device, and comprising a second terminal. The first voltage providing device is configured to provide a driving voltage at the second terminal of the first voltage providing device via providing a voltage drop to the initial driving voltage.

I/O driving circuit and control signal generating circuit

A control circuit comprising a driving circuit, which comprises a voltage adjusting circuit for generating a control voltage, and comprises a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. The control circuit further comprises: a candidate voltage selecting circuit, for outputting one of a plurality of candidate voltages; and a voltage selecting circuit, for outputting one of the candidate voltage output from the candidate voltage selecting circuit and a ground voltage as the bias voltage.

Control circuit and control system

One embodiment of the present application discloses a control circuit comprising a driving circuit which comprises a voltage adjusting circuit, a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. A control system comprising the control circuit is also disclosed.

A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.

Clock tree circuit and memory controller

A clock tree circuit includes a clock source and a tree circuit. The clock source generates a signal. The tree circuit at least includes five driving units and a metal connection element. A first driving unit has an input terminal for receiving the signal, and an output terminal coupled to a first node. A second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node. A third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node. A fourth driving unit has an input terminal coupled to the second node. A fifth driving unit has an input terminal coupled to the third node. The metal connection element is coupled between the second node and the third node, and configured as a short-circuited element.

A level shifter circuit includes a level shifter unit and a first controlling unit. The level shifter unit has an input node for receiving an input signal having a predetermined level, an output node for outputting an output signal having a desired level and a complementary output node for outputting a complementary output signal complementary to the output signal. The first controlling unit is coupled to the level shifter unit and has a first transistor coupled between the complementary output node and a first control node for receiving a first control signal and a second transistor coupled between the input node for receiving the input signal and a ground.

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Chiayi County, Taiwan

Chen-Feng Chiang