Nan Ya Technology Corporation

Inventec Corp.

Inventec (pudong) Technology Corporation

Chen-Chou Huang

Sheng-Wei Yang

Cheng-Chih Huang

Neng-Tai Shih

Sheng-Tsung Chen

Chung-Yuan Lee

Chang-Rong Wu

Chien-Mao Liao

Sweehan J H Yang

Tzu-En Ho

Wen-Sheng Liao

Chih-How Chang

Hsueh-Liang Chen

Yan-Yue Yin

A value-added content providing method for a computer system includes receiving an input message indicating to present a pop-up window in a display area of the computer system; obtaining a content area in the display area according to the input message; analyzing the content area to generate an analysis content; and providing and displaying a value-added content in the pop-up window according to the analysis content.

Value-added content providing method and computer system thereof

An adjusting method of a virtual keyboard adapted to a first touch device is disclosed. The first touch device displays a virtual keyboard with several keys. The adjusting method includes the following operations: adjusting a position and a size of the virtual keyboard displayed on the first touch device according to an operating range of a user; collecting several first click points on the virtual keyboard and one of the keys corresponding to the first click points; analyzing several press distributions of the keys according to the first click points; determining one of the keys corresponding to a second click point according to the press distributions and center points of the keys; transmitting the press distributions and the position and the size of the virtual keyboard to a server; and transmitting the press distributions and the position and the size of the virtual keyboard to a second touch device.

Adjusting method of a virtual keyboard and touch device

A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.

Method for isolation layer for a vertical DRAM

A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the level of the surface of the conducting layer to form a groove between the conducting layer and the trench. The groove is filled with a doped conducting layer. The dopant in the doped conducting layer is diffused to the semiconductor substrate in an ion diffusion area as a buried strap. The conducting layer and the doped conducting layer are etched below the ion diffusion area. A top trench insulating layer is formed on the bottom of the trench, wherein the top trench insulating layer is lower than the ion diffusion area.

Method for forming a self-aligned buried strap in a vertical memory cell

A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.

Method for fabricating trench isolation

A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined depth, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.

A method of forming a single sided conductor and a semiconductor device having the same is provided. The method includes providing a substrate having an opening. The opening exposes a sidewall and an opening base surface. A single sided silicon layer adjacent to the sidewall in the opening. The single sided silicon layer exposes a portion of the opening base surface. The single sided silicon layer is implanted with fluorine-containing ions. The substrate and the single sided silicon layer is thermally oxidized to form a thermal oxide layer in the opening.

Growing community of inventors

Taipei, Taiwan

Chen-Chou Huang