Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Chiu Huang

Dian-Hau Chen

Hsiang-Ku Shen

Yuan-Yang Hsiao

Yen-Ming Chen

Chih-Fan Huang

Tsung-Chieh Hsiao

Liang-Wei Wang

Chih-Pin Chiu

Chun-Chang Liu

Wen-Chiung Tu

Kuo-Chang Huang

Fu-Peng Lu

Chien-Hua Huang

Mao-Nan Wang

Yu-Jen Wang

Chung-Te Lin

Zhiqiang Wu

Kai-Wen Cheng

Szu-Ping Tung

Cheng-Hao Hou

Hung-Chao Kao

Kuo-An Liu

Guan-Yao Tu

Kai Tak Lam

Hsiang-Lun Kao

Po-Sheng Lu

Chang-Lin Yang

Ying-Yao Lai

Chih-Hsin Yang

Chih-Chuan Su

Tzu-Ting Liu

Wen-Tzu Chen

Chen-Te Chu

Yu-En Jeng

A method for forming a semiconductor structure includes forming a metal-insulator-metal (MIM) structure between first passivation layers over a substrate. The method also includes forming a via structure through the MIM structure and the first passivation layers. The method also includes planarizing the via structure. The method also includes forming an RDL structure over the via structure. The method also includes forming a second passivation layer over the RDL structure and the first passivation layers.

Semiconductor structure and method for forming the semiconductor structure

A device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. The second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. The device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.

Back-end-of-line passive device structure

A semiconductor packaging structure includes a first passivation layer, a capacitor structure, and a second passivation layer. The capacitor structure is disposed on the first passivation layer. The second passivation layer is disposed on the capacitor structure opposite to the first passivation layer. The second passivation layer has a compressive stress that is smaller than −0.3 GPa.

Semiconductor packaging structure and method for manufacturing the same

In a method of manufacturing a semiconductor device including a magnetic random access memory (MRAM) cell, a first layer made of a conductive material is formed over a substrate. A second layer for a magnetic tunnel junction (MTJ) stack is formed over the first conductive layer. A third layer is formed over the second layer. A first hard mask pattern is formed by patterning the third layer. The MTJ stack is formed by patterning the second layer by an etching operation using the first hard mask pattern as an etching mask. The etching operation stops at the first layer. A sidewall insulating layer is formed over the MTJ stack. After the sidewall insulating layer is formed, a bottom electrode is formed by patterning the first layer to form the MRAM cell including the bottom electrode, the MTj stack and the first hard mask pattern as an upper electrode.

Magnetic random access memory and manufacturing method thereof

A method includes forming a magnetic tunnel junction (MTJ) stack over a substrate. The MTJ stack including a top magnetic layer, a barrier layer, and a bottom magnetic layer. The method also includes patterning the top magnetic layer in a first etch process, after the patterning of the top magnetic layer depositing a spacer on sidewalls of the patterned top magnetic layer, and patterning the bottom magnetic layer in a second etch process.

Semiconductor memory device with spacer protection and method for forming same using multi-step patterning

Passive devices are provided. In an embodiment, a passive device includes a substrate comprising a first region and a second region, a first lower contact feature and a second lower contact feature in a dielectric layer and directly over the first region and the second region, respectively, a first vertical stack of conductive features disposed over the first region, a metal-insulator-metal (MIM) capacitor disposed over the second region and comprising a vertical stack of conductor plates, a first contact via extending through the first vertical stack of conductive features and electrically coupled to the first lower contact feature, and a second contact via extending through a portion of the vertical stack of conductor plates and electrically coupled to the second lower contact feature. A number of conductive features penetrated by the first contact via is different than a number of conductor plates penetrated by the second contact via.

Semiconductor structures and methods of forming the same

An exemplary method includes forming a multilayer interlevel dielectric (ILD) layer having a metal-containing dielectric layer (e.g., an aluminum oxide layer) between a first dielectric layer and a second dielectric layer and forming a bottom electrode via in the multilayer ILD layer. The method further includes forming a bottom electrode layer over the bottom electrode via, magnetic tunnel junction (MTJ) layers over the bottom electrode layer, and a top electrode layer over the MTJ layers. The bottom electrode layer, the MTJ layers, and the top electrode layer are etched to form a bottom electrode, an MTJ element, and a top electrode, respectively, of a magnetoresistive random-access memory (MRAM). The etching, such as an ion beam etch, forms a recess in the multilayer ILD layer that extends to the metal-containing dielectric layer of the multilayer ILD layer. In some embodiments, the etching extends the recess into and/or through the metal-containing dielectric layer.

Magnetoresistive random-access memory (MRAM) structure for improving process control and method of fabricating thereof

A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack. The MIM stack includes at least one lower conductor plate layer, a first insulator layer disposed over the at least one lower conductor plate layer, a first conductor plate layer disposed over the first insulator layer, a second insulator layer disposed over the first conductor plate layer, and a second conductor plate layer disposed over the second insulator layer. The device structure further includes a ground via extending through and electrically coupled to a first ground plate in the first conductor plate layer and a first via extending through and electrically coupled to a high voltage plate in the second conductor plate layer. The first ground plate vertically overlaps the high voltage plate and the second insulator layer is different from the first insulator layer.

High voltage passive device structure

A method for forming a semiconductor memory structure includes forming an MTJ stack over a substrate. The method also includes etching the MTJ stack to form an MTJ device. The method also includes depositing a metal layer over a top surface and sidewalls of the MTJ device. The method also includes oxidizing the metal layer to form an oxidized metal layer. The method also includes depositing a cap layer over the oxidized metal layer. The method also includes oxidizing the cap layer to form an oxidized cap layer. The method also includes removing an un-oxidized portion of the cap layer.

Semiconductor memory structure and method for forming the semiconductor memory structure

Structures of a semiconductor device structure are provided. The semiconductor device structure includes a first insulating layer formed over a semiconductor substrate and an interconnect structure formed in the first insulating layer. The semiconductor device structure also includes a second insulating layer formed over the first insulating layer and a capacitor device embedded in the second insulating layer. The capacitor device includes a first capacitor electrode layer electrically connected to the interconnect structure, a capacitor insulating stack formed over the first capacitor electrode layer and a second capacitor electrode layer formed over the capacitor insulating stack. The capacitor insulating stack includes first layers alternatingly stacked with second layers. The dielectric constant of the first layer is different than the dielectric constant of the second layer.

Capacitor device with multi-layer dielectric structure

A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack that includes a plurality of conductor plate layers interleaved by a plurality of insulator layers. The MIM stack includes a first region and a second region and the first region and the second region overlaps in a third region. The MIM stack further includes a first via passing through the first region and electrically coupled to a first subset of the plurality of conductor plate layers, a second via passing through the second region and electrically coupled to a second subset of the plurality of conductor plate layers, and a ground via passing through the third region and electrically coupled to a third subset of the plurality of conductor plate layers.

Back-end-of-line passive device structure having common connection to ground

Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.

Reduction of cracks in passivation layer

A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.

Magnetic tunnel junction device and method of forming the same

A semiconductor device includes a transistor structure disposed over a substrate, a first interlayer dielectric (ILD) layer disposed over the transistor structure, a second ILD layer disposed over the first ILD layer, and a first resistor wire disposed on the second ILD layer, and a second resistor wire disposed on the second ILD layer. A sheet resistance of the first resistor wire is different from a sheet resistance of the second resistor wire.

Method of manufacturing a semiconductor device and a semiconductor device

Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.

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Taichung, Taiwan

Chen-Chiu Huang