United Microelectronics Corp.

Silicon Integrated Systems Corporation

Powerchip Semiconductor Corporation

Powerchip Semiconductor Manufacturing Corporation

United Microelectronics Coporation

Chen-Chiu Hsue

Gary Y Hong

Ming-Tzong Yang

Shyh-Dar Lee

Sun-Chieh Chien

Chen-Hui Chung

Joe Ko

Anchor Chen

Shing-Ren Sheu

Water Lur

Kuan-Cheng Su

Chung-Yuan Lee

Yi-Chung Sheng

Cheng-Han Huang

Da Sung

Te-Sun Wu

Edward Houn

Chien-Chih Du

Leo Wang

Tzong-Shien Wu

Lee Chung Yuan

Ming-Jeng Huang

Jen-Hann Tsai

Shing-Ren Shev

Jih-Wen Chou

Chun-Yen Chang

Ko-Hsing Chang

Tung-Po Chen

Hwi-Huang Chen

Chih-Hung Lin

Lung Chen

Jengping Lin

Cheng-Hui Chung

Hung-Kwei Liao

Yu-Ju Liu

Ching-Hua Chen

Ming-Hua Liu

Tung-Ming Lai

H J Wu

Kai-An Hsueh

Hong J Wu

Teng-Feng Wang

Lawrence Y Lin

Shun-Tsung Yu

Ming-Yuan Lin

Hsun-Kuei Chan

Min-Tzong Yang

Sun-Cheih Chien

Yi-Chung Shen

Han-Chao Lai

Ming-Te Huang

Peter Chang

Bing-Chen Ji

Li-Tsen Jiang

A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.

Non-volatile memory device and manufacturing method thereof

A memory structure including a substrate, a charge storage layer, a first gate, a first dielectric layer, and a second dielectric layer is provided. The substrate includes a memory cell region. The charge storage layer is located on the substrate in the memory cell region. The charge storage layer has a recess. The charge storage layer has a tip around the recess. The first gate is located on the charge storage layer. The first dielectric layer is located between the charge storage layer and the substrate. The second dielectric layer is located between the first gate and the charge storage layer.

Memory structure and manufacturing method thereof

A photosensitive device having at least an insulator layer including a plurality of photoreceiving regions disposed on a substrate. A plurality of conductive patterns is disposed on the insulator layer without covering the photoreceiving regions. A flattened dielectric layer is disposed on the conductive patterns and the insulator layer, wherein a surface of the dielectric layer is higher than a surface of the conductive patterns in a range between 2000 &#x212b; to 4000 &#x212b;.

Photosensitive device

A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region. The p-type doped region passes through the junction between the drain region and the p-type pocket doped region but is separated from the spacer by a distance. The contact plug is set up over the drain region and is electrically connected to the p-type doped region.

Flash memory cell and manufacturing method thereof

A method of fabrication of a photosensitive device is disclosed. A substrate with at least an insulator layer formed thereon is provided. The insulator layer comprises a plurality of photoreceiving regions, and a plurality of conductive patterns are formed thereon without covering the photoreceiving regions. A dielectric layer is formed on the insulator and the conductive patterns, and polished by CMP thereof. The dielectric layer comprises a first dielectric layer formed by PECVD and a second dielectric layer formed by HDPCVD.

Method of fabricating a photosensitive structure

A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined to form the floating gate is exposed and then a cap layer is formed thereon. The first patterned mask layer is removed and then a second conductive layer and a second patterned mask layer are formed over the substrate. A word line and a floating gate are formed using the second patterned mask layer and the cap layer as a mask. The second patterned mask layer is removed and then source/drain regions are formed in the substrate on both sides of the word line and the floating gate and between the word line and the floating gate.

Method for manufacturing one-time electrically programmable read only memory

Flash memory cell

A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.

Dual damascene process using metal hard mask

A method for improving adhesion of a low k dielectric to a barrier layer. A substrate covered by an insulating layer having copper interconnects is provided. A sealing layer is formed on the copper interconnects and the insulating layer. A plasma treatment is performed on the sealing layer by a reaction gas including at least one of CO , NH , NO , SiH , trimethylsilane, and tetramethylsilane. A low k dielectric layer is formed on the sealing layer.

Method for improving adhesion of a low k dielectric to a barrier layer

A capacitor in which the lower electrode and an interconnect line are located at the same level. The capacitor includes a first conductive line and a second conductive line on a substrate located at the same level, wherein the second conductive line defines a capacitor region and is used as a lower electrode of the capacitor; an insulating layer on the substrate, the first conductive line, and the second conductive line; and a third conductive line on the insulating layer in the capacitor region such that the third conductive line is used as an upper electrode of the capacitor. Since the lower electrode and an interconnect line can be in-situ (concurrently) formed to be located at the same level, one mask can be omitted compared with the conventional method, and production costs can be reduced.

Capacitor with lower electrode located at the same level as an interconnect line

Disclosed is a method for forming selective protection layers on copper interconnects in a damascene process. A copper layer is deposited overlying a dielectric layer and filling interconnect trenches which are previously formed in the dielectric layer. The excess copper layer is polished by a chemical mechanical polishing process with a slurry comprising an aluminum organic substance. The aluminum organic substance reacts with copper via annealing to selectively form aluminum-copper alloys on the copper interconnects. The aluminum-copper alloys are then oxidized to form aluminum oxide protection layers capping the copper interconnects.

Method for forming selective protection layers on copper interconnects

A method for fabricating a polysilicon capacitor. The method includes the following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is patterned to concurrently form a first polysilicon line and a second polysilicon line. The second polysilicon line defines a polysilicon capacitor region and is used as a lower electrode of the polysilicon capacitor. Next, an insulating layer is formed conformably on the substrate, the first polysilicon line, and the second polysilicon line. A first dielectric layer is formed on the insulating layer, which is then subjected to planarization treatment such that the planarization treatment ends up to the insulating layer. Finally, a third polysilicon line is formed on the insulating layer in the polysilicon capacitor region such that the third polysilicon line is used as an upper electrode of the polysilicon capacitor. Since the lower electrode and the interconnect line can be in-situ (concurrently) formed, one mask can be omitted compared with the conventional method, and production costs can be reduced.

Method for fabricating polysilicon capacitor

A metal capacitor in damascene structures is provided. A first Cu wire and a second Cu wire are located in a first insulator. A first sealing layer is located on the first and the second Cu wires. A second insulator is located on the first sealing layer. A third insulator is located on the second insulator, and acting as an etch stop layer. A first Cu plug and a second Cu plug are located in the first sealing layer, the second insulator and the third insulator. A capacitor is located on the third insulator and the first Cu plug, the capacitor having an upper electrode, a capacitor dielectric and a bottom electrode with the same pattern each other, wherein the bottom electrode is connected to the first Cu wire through the first Cu plug. A conducting wire is located on the third insulator and the second Cu plug, wherein the conducting wire is connected to the second Cu wire through the second Cu plug. A fourth insulator is located on the conducting wire. A fifth insulator with a flat surface is located on the upper electrode, the fourth insulator and the third insulator. A plurality of dual damascene structures including a third plug, a fourth Cu plug, a third Cu wire and a fourth Cu wire are located in the fifth insulator, wherein an upper electrode of the capacitor is connected to the third Cu wire through the third Cu plug, and the conducting wire is connected to the fourth Cu wire through the fourth Cu plug. A second sealing layer is located on the third and fourth Cu wires.

Metal capacitor in damascene structures

A method for manufacturing a MOS device with improved well control stability. The method includes the steps of providing a semiconductor substrate; forming a gate electrode according to a critical dimension on the semiconductor substrate, wherein the gate electrode comprises a gate oxide layer and a conducting gate; inspecting a real dimension of the conducting gate; determining a thickness of subsequently formed conducting gate spacers according to the real dimension of the conducting gate, such that variations of electric characteristics of the device affected by the critical dimension of the conducting gate are reduced; and forming the conducting gate spacers with the determined thickness on sidewalls of the gate electrode.

Method for manufacturing a MOS device with improved well control stability

This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor is composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.

Metal capacitors with damascene structures

Growing community of inventors

Hsin-chu, Taiwan

Chen-Chiu Hsue