Hughes Aircraft Company

Other

Raytheon Company

Hughes Electronics Corporation

Chen-Chi P Chang

Mei F Li

Maw-Rong Chin

Joseph E Farb

Truc Q Vu

James S Cable

Kuan Y Liao

A silicon-based radiation-hard cryo-CMOS CCD process suitable for fabrication of devices ( ) with sub-micron feature sizes. A re-oxidized nitride/oxide (RONO) layer ( ) is preserved in the CCD area ( ) while plasma etching is used to define polysilicon 1 gates ( ) in the active FET area of the device. Thereafter, a wet chemical etching process, which does not destroy the integrity of the RONO layer ( ) in the CCD area, is carried out. A channel stop ( ) is formed after the field oxidation step in the active FET area to reduce the space required for minimum diode breakdown voltage between the n source/drain region and the p channel stop.

Radiation-hard silicon cryo-CMOS process suitable for charge-coupled devices, and a device made according to this process

A radiation-hard isoplanar cryo-CMOS process suitable for submicron device fabrication reduces channel length to submicron levels. A channel stop (52) is formed after a first polysilicon gate (50) is formed to reduce the space between a n-/n+ source/drain region (67, 68) and the channel-stop region (52). Double gate oxidation steps are performed to increase polyoxide thickness. A thermal oxide masking step is carried out to obtain a thin layer of gate oxide under a second polysilicon gate (60A) for CMOS devices. The process includes two different second polysilicon masking steps to provide dimension control of second polysilicon gates (60A) and to remove bridging of the second polysilicon where the second polysilicon layer (58) is over the first polysilicon layer (48).

Radiation-hard isoplanar cryo-CMOS process suitable for sub-micron

A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both a fabrication and structural complexity favorably comparable to conventional CMOS devices which are not radiation-hard. A method for fabricating the device is disclosed.

Radiation-hard, low power, sub-micron CMOS on a SOI substrate

The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions. The fabrication process and thinness of the latch transistor gate improve the linewidth control of other transistors formed on the substrate and the latch transistor by avoiding overetching and reducing the normal etching time for the latch gate, respectively.

Nonvolatile memory device

Method for fabricating gate structure for nonvolatile memory device

Each unit cell (10) of a flash EEPROM array (50) includes a source (18), a drain (20) and a channel (22) formed in a substrate (12). A thin tunnel oxide layer (32) is formed over the substrate (12) and P-Well (14). A bifurcated floating gate (34) is formed on the tunnel oxide layer (32) overlying the channel (22) , and includes a program arm (34a) which overlaps the drain (20), an erase arm (34b) which overlaps the source (18) and a base (34c) which extends around an end of the channel (22) and interconnects the program and erase arms (34a,34b). A thick gate oxide layer (36,36a) is formed over the floating gate (34), and a control gate (38) is formed over the gate oxide layer (36,36a). A central section of the control gate (38) which overlies a gap (34d) between the program and erase arms (34a, 34b) provides threshold voltage control for erasure. The erase arm (34b) spans the entire width of the channel (22), enabling erasure with low applied voltages. The bifurcated floating gate design automatically compensates for alignment error during fabrication such that the relative areas of the channel (22) which underlie the program/erase arms (34a, 34b) and gap (34d) are independent of the location of the gap (34d).

Flash EEPROM cell and array with bifurcated floating gates

A flash or block erase electrically erasable programmable read-only memory (EEPROM) cell (10) includes a substrate (12) having a channel region (22), and a source (28) and a drain (32) formed in the substrate (12) on opposite sides of the channel region (22). A first oxide layer (19), a floating gate (20), a second oxide layer (24) and a control gate (26) are formed over the channel region (22). The cell (10) is programmed by hot electron injection from the drain (32) into the floating gate (20), and erased by Fowler-Nordheim tunneling from the floating gate (20) to the source (28). A gap (36) is provided between a sidewall (20a) of the floating gate (20) and the drain (32) to increase the electric field in the drain depletion region. An oxide sidewall spacer (38) is formed on the first oxide layer (19) in the gap (36) which traps electrons. The gap (36) and sidewall spacer (38) increase the hot electron injection efficiency, and enable programming to be accomplished at high speed, with low applied voltages and at high temperatures.

Flash EEPROM cell having gap between floating gate and drain for high

Each unit cell (10) of a flash EEPROM array (50) includes a control gate (38) having a section (38b) disposed in series between a program section (34a) of a floating gate (34) and a source (18) to provide threshold voltage control for erasure. The floating gate (34) further has an erase section (34b) which extends from the program section (34a) around an end of a channel (22) to the source (18). A thin tunnel oxide layer (32) is formed between an end portion (34c) of the erase section (34b) and an underlying portion of the source (18) which enables the floating gate (34) to be erased by Fowler-Nordheim tunneling from the end portion (34c) through the oxide layer (32) to the source (18) with low applied voltages.

Split-gate flash EEPROM cell and array with low voltage erasure

Complimentary metal oxide silicon transistors fabricated on silicon-on-insulator substrates are configured to allow separately controllable and independent backgate bias for adjacent complimentary devices on the same substrate. By means of deep implantation of boron, a backgate bias P- well (26,126) is positioned on the N-substrate (17,117) at a front surface of the N- substrate behind the N channel transistor of a complimentary pair. The backgate bias P- well (26,126) is provided with an electrical contact (48,148) at the front of the device, as is the N- silicon substrate to enable independent application of separate bias voltage of different polarities and appropriate magnitude.

Control of backgate bias for low power high speed CMOS/SOI devices

High speed silicon-on-insulator radiation hardened semiconductor devices and a method of fabricating same. Starting with a SIMOX wafer (10) having a layer of silicon (12) on a layer of buried oxide (11), P-well and N-well masks are aligned to an oversized polysilicon mask (16). This produces relatively thick source and drain regions (18) and relatively thin gate regions (17). The relatively thick source and drain regions (18) educe the risk of dry contact etch problems. N-channel and P-channel threshold voltages are adjusted prior to the formation of active areas, thus substantially eliminating edge and back channel leakage. A sacrificial thin oxide layer (21) is employed in fabricating the N-well and P-well implants so that both front and back channel threshold voltage adjustments are controlled. Good control of doping profiles is obtained, leading to excellent threshold voltage control and low edge and back channel leakages. The speed of devices fabricated using the method of the present invention is high due to reduced capacitances resulting from thinner silicon-on-insulator films. The present invention is fabricated using present equipment and available technology, and provides an easy, straight forward and cost-effective process to fabricate very high speed CMOS devices which are latch-up free and radiation hardened.

High speed silicon-on-insulator device

Highly doped N- and P-type wells (16a, 16b) in a first silicon layer (16) on an insulator layer (14) of a SIMOX substrate (10). Complementary MOSFET devices (52,54,58,62) are formed in lightly doped N- and P-type active areas (22a, 22b) in a second silicon layer (22) formed on the first silicon layer (16). Adjacent active areas (22a, 22b) and underlying wells (16a, 16b) are isolated from each other by trenches (36,78) filled with a radiation-hard insulator material. Field oxide layers (42,64) are formed of a radiation-hard insulator material, preferably boron phosphorous silicon dioxide glass, over the surface of the second silicon layer (22) except in contact areas (68) of the devices (52,54,58,62). The devices (52,54,58,62) are formed in the upper portions of the active areas (22a, 22b), and are insensitive to the interfacial states of the SIMOX substrate (10). The buried wells (16a, 16b ) under the active areas (22a, 22b) have low resistance and enable the devices (52,54,58,62) to have high snap-back voltages. The absence of sharp edges also eliminates edge leakage upon high dosage irradiation, thus producing devices that are more radiation-resistant.

Radiation-hard, high-voltage semiconductive device structure fabricated

High speed silicon-on-insulator radiation hardened semiconductor devices and a method of fabricating same. Starting with a SIMOX wafer (10) having a layer of silicon (12) on a layer of buried oxide (11), P-well and N-well masks are aligned to an oversized polysilicon mask (16). This produces relatively thick source and drain regions (18) and relatively thin gate regions (17). The relatively thick source and drain regions (18) reduce the risk of dry contact etch problems. N-channel and P-channel threshold voltages are adjusted prior to the formation of active areas, thus substantially eliminating edge and back cannel leakage. A sacrificial thin oxide layer (21) is employed in fabricating the N-well and P-well implants so that both front and back channel threshold voltage adjustments are controlled. Good control of doping profiles is obtained, leading to excellent threshold voltage control and low edge and back channel leakages. The speed of devices fabricated using the method of the present invention is high due to reduced capacitances resulting from thinner silicon-on-insulator films. The present invention is fabricated using present equipment and available technology, and provides an easy, straight forward and cost-effective process to fabricate very high speed CMOS devices which are latch-up free and radiation hardened.

High speed silicon-on-insulator device and process of fabricating same

Methods of fabricating heavily doped edges of mesa structures in silicon-on-sapphire and silicon-on-insulator semiconductor devices. The methods are self-aligning and require a minimum of masking steps to achieve. The disclosed methods reduce edge leakage and resolve N-channel threshold voltage instability problems. Mesa structures are formed that comprise N-channel and P-channel regions having a thermal oxide layer deposited thereover. A doping layer of borosilicate glass, or alternatively, an undoped oxide layer that is subsequently implanted, is deposited over the mesa structures. In the first method, the doping layer is etched by means of an anisotropic plasma etching procedure to form oxide spacers at the edges of the mesa structures. The doping layer is removed from the N-mesa structures using an N-channel mask and wet oxide etching procedure. The structure is then heated to a relatively high temperature to drive the dopant into the edges of the N-channel mesa structures. The protective layers are then removed by a wet etching procedure. The semiconductor device is fabricated to completion in a conventional manner thereafter. In the second method, a nitride layer is deposited over the mesa structures and thermal oxide layer. A thin oxide layer, which is generally deposited by means of a chemical vapor deposition procedure, is deposited over the silicon nitride layer. The formed structure is then processed to expose the N-channel mesa structures. This is accomplished using an N-well mask, the oxide layer is etched to expose the silicon nitride layer over the N-channel, and the nitride layer covering the N-channel is removed by means of hot phosphoric acid using the oxide layer as a mask. The doping layer is then deposited over the mesa structures. This doping layer is then heated to drive the dopant/implant into the edges of the N-channel mesa structures. The doping layer is then removed by wet oxide etching, the nitride layer is removed by rinsing in hot phosphoric acid and the thermal oxide layer is removed by a wet oxide etching procedure. The semiconductor device is again fabricated to completion in a conventional manner thereafter.

Edge doping processes for mesa structures in SOS and SOI devices

A radiation hard, high voltage integrated circuit device fabrication process. A silicon substrate is implanted with ions that form a buried layer and an epitaxial layer of silicon is grown thereover. The structure is heated to form adjacent N- and P-channel regions. Channel stops are then formed surrounding the respective channel regions. After forming the channel stops, the substrate is masked and predefined dopant ions are implanted into the source and drain regions of the respective wells in the substrate. The distribution of the dopant ions therein are adjusted to have a predetermined doping profile that defines a graded junction. Then the substrate is heated to a relatively high temperature to provide a high temperature drive cycle that forms a desired graded junction profile. A field oxide layer is then deposited on the substrate, and it is masked and etched to define active areas. A gate oxide layer is grown on the substrate above the active areas, and polysilicon gates are formed thereon. Finally, dopant ions are implanted into source and drain regions using the polysilicon gates and field oxide layer as a mask. This forms the completed semiconductor devices. The devices fabricated using this process have N.sup.+ (source and drain regions) to P-well and complementary P.sup.+ to N-well junction breakdown voltages in the 10-12 volt range, and the radiation performance of the devices is not degraded.

Process for fabricating radiation hard high voltage devices

A method of fabricating high speed, low leakage, radiation hardened integrated circuit semiconductor devices. In accordance with the method a SIMOX (separation by ion implantation of oxygen) wafer is masked with a separation mask to form silicon islands. The separation mask forms groups of N-channel and P-channel devices that are isolated from each other. The N- and P-channel device separation assists in preventing device latch-up. N- and N-channel devices are isolated by controlling the process due to high field inversion thresholds and radiation hardened field oxide to eliminate any channel-to-channel leakage current after high dosage irradiation. A relatively thin gate oxide layer is formed over the islands, and the island edges are covered with phosphoroborosilicate glass deposited at a relatively low temperature (850.degree. C.) to eliminate sharp island edges and hence edge leakage. The use of SIMOX substrate materials, phosphoroborosilicate glass and thin oxide provides the benefits of improved speed and reduced leakage due to intrinsic oxide isolation, shallow wells and source and drain junctions. The use of a thin thermal oxide layer and phosphoroborosilicate glass eliminates the edge leakage and channel-to-channel leakage upon high dosage irradiation, thus providing improved radiation hardness. The method of the present invention provides for devices having stable field behavior after irradiation. The method produces radiation hardened devices that exhibit high speed and reliability and which are stable when irradiated with up to a 10 MRad dosage level.

Growing community of inventors

Newport Beach, CA, United States of America

Chen-Chi P Chang