Intel Corporation

Chen-Chi Kuo

Sridhar Lakshmanamurthy

Prashant R Chandra

Rohit Natarajan

Jaroslaw Sydir

Gilbert M Wolrich

Wajdi K Feghali

Mark B Rosenbluth

Alok Kumar

Uday Ramakrishna Naik

Bradley A Burres

Kamal J Koshy

Jeen-Yuan Miin

Senthil Nathan Arunachalam

James D Guilford

Michael E Kounavis

Raj S Yavatkar

Kin-Yip Liu

Raymond Ng

Harrick M Vin

Wilson Y Liao

Chang-Ming P Lin

Subramanian Anand

Pun Yim

We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory interface to manipulate data from at least two memory channels, each memory channel corresponding to a portion of a distributed memory, responsive to the predetermined memory access command. The memory interface includes a plurality of memory controllers coupled to the command bus, each memory controller being operable to control a corresponding memory channel responsive to the predetermined memory access command, and a push arbiter coupled to each memory controller. The push arbiter being is operable to merge and align data retrieved responsive to each split read align command.

Apparatus and method to merge and align data from distributed memory controllers

A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.

Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor

A method and apparatus for two-stage packet classification. In the first stage, which may be implemented in software, a packet is classified on the basis of the packet's network path and, perhaps, its protocol. In the second stage, which may be implemented in hardware, the packet is classified on the basis of one or more transport level fields of the packet. An apparatus of two-stage packet classification may include a processing system for first stage code execution, a classification circuit for performing the second stage of classification, and a memory to store a number of bins, each bin including one or more rules.

Apparatus and method for two-stage packet classification using most specific filter matching and transport level sharing

Provided is an engine for comparing a key with rules having defined ranges. A key is received and a rule is accessed including a high and low values defining a range. The key is concurrently compared with the high and low values to determine whether the key falls within a range defined by the high and low values an indication is made in status information the rule in response to the key falling within the defined range of the rule. An additional iteration of accessing a next rule is performed to concurrently compare the key with the high and low values of the next rule, and indication is made in the status information of the next rule in response to the key falling within a range defined by the next rule.

Engine for comparing a key with rules having high and low values defining a range

Methods, software and systems for handling parity errors in flow control channels are presented. A network processor is provided having a flow control message First In First Out (FIFO) buffer and wherein the FIFO buffer includes a parity field. The network processor is included as either or both of an Ingress network processor and an Egress network processor and is used within a CSIX system or an NPSI NPE system.

Method and apparatus to handle parity errors in flow control channels

According to some embodiments, a processing element includes (i) a next neighbor register to receive information directly from a previous processing element in a series of processing elements, and (ii) a previous neighbor register to receive information directly from a next processing element in the series.

Processing element with next and previous neighbor registers for direct data transfer

Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.

Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches

A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.

Memory controller for padding and stripping data in response to read and write commands

In general, in one aspect, the disclosure describes a method of assembling a packet in memory. The method includes reading data included in a first segment of a packet divided into multiple segments and issuing a command to a memory controller that causes the memory controller to shift and write a subset of the read data to a memory coupled to the memory controller. The method also includes saving the remainder of the read data as a first residue, retrieving data included in a second segment of the packet, and writing at least a portion of the retrieved data and the first residue to the memory.

Packet assembly

An arrangement of buffer in a memory unit including a plurality of memory banks may store information in rows that span the memory banks. Moreover, a processor may be adapted to (i) establish a plurality of buffers to be associated with the memory unit, wherein the size of each buffer is less than the width of a memory bank, and (ii) arrange for a selected buffer to begin in a memory bank other than a memory bank in which a previously selected buffer begins.

Network packet buffer allocation optimization in memory bank systems

According to some embodiments, an arrangement of buffers in memory banks is provided.

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Pleasanton, CA, United States of America

Chen-Chi Kuo