Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Cheng Kuo

Chen-Shien Chen

Yao-Chun Chuang

Chih-Hua Chen

Chita Chuang

Hung-Jui Kuo

Zi-Jheng Liu

Ching-Wen Hsiao

Kai-Ming Ching

Hao-Juin Liu

Ming Hung Tseng

Tzuan-Horng Liu

Wen-Wei Shen

Tsung-Shu Lin

Tsung-Hsien Chiang

Ming-Hong Cha

Chung-Shi Liu

Yu-Hsiang Hu

Shang-Yun Tu

Chen Chen-Shien

Chen-Hua Douglas Yu

Ming-Fa Chen

Ming-Da Cheng

Chih-Wei Lin

Meng-Wei Chou

Yu-Chen Hsu

Jo-Lin Lan

Shang-Yun Hou

Sih-Hao Liao

Rung-De Wang

Hao Chun Liu

Shin-Puu Jeng

Jen-Cheng Liu

Wei-Cheng Wu

Hung-Chang Hsieh

Shih-Shiung Chen

Chang-Chia Huang

Hung-Chih Chen

Hsiu-Ping Wei

Ho-Ku Lan

Dun-Nian Yaung

Chia-Shiung Tsai

Wen-Chih Chiou

Tin-Hao Kuo

Han-Ping Pu

Shou-Gwo Wuu

Tsu Shih

Hua-Tai Lin

Chia-Hui Lin

Ming-Tan Lee

Han-Hsiang Huang

Bai-Yao Lou

De-Yuan Lu

Ru-Ying Huang

Dean Wang

Young-Chang Lien

Ding-Chung Lu

Cheng Hung Shen

Yao-Chun Chunag

Shih-Hao Liao

Kuo-Ching “Steven” Hsu

A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

Semiconductor package and method of fabricating semiconductor package

A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

Stress reduction apparatus and method

A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

Semiconductor device

A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

Package structures and methods for forming the same

A semiconductor device includes a conductive pad having a first width. The semiconductor device includes a passivation layer over the conductive pad, wherein the passivation layer directly contacts the conductive pad. The semiconductor device includes a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The semiconductor device includes an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device includes a conductive pillar on the UBM layer.

Semiconductor device and package assembly including the same

A semiconductor package includes a first chip, a first chip and a molding compound. The first chip has a first via protruding from the first chip. The second chip has a second via protruding from the second chip, wherein a thickness of the first chip is different from a thickness of the second chip. The molding compound encapsulates the first chip, the second chip, the first via and the second via, wherein surfaces of the first via, the second via and the molding compound are substantially coplanar.

Semiconductor packages

A semiconductor package includes a first chip, a plurality of through vias and an encapsulant. The first chip has a first via and a protection layer thereon. The first via is disposed in the protection layer. The through vias are disposed aside the first chip. The encapsulant encapsulates the first chip and the plurality of through vias. A surface of the encapsulant is substantially coplanar with surfaces of the protection layer and the plurality of through vias.

Semiconductor packages and manufacturing methods thereof

The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Bonded structures for package and substrate

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Chu-Pei, Taiwan

Chen-Cheng Kuo