Alibaba Group Holding Limited

Advanced New Technologies Co., Ltd.

C-Sky Microsystems Co., Ltd.

Hangzhou Huawei-3Com Technology Co., Ltd

Hangzhou Star Lighting Corp., Ltd.

Yutou Technology Co., Ltd.

Hangzhou Huamai Medical Technology Co., Ltd.

Chen Chen

Dongqi Liu

Chang Liu

Hui Li

Lin Wang

Le Song

Xiaofu Chang

Guanyin Zhu

Xin Huang

Chunyang Wen

Zhibang Ge

Yiguang Wang

Lei Huang

Chaojun Zhao

Dingyan Wei

Haowen Chen

Lei Zhang

Feng Lin

Yu Ying Wang

Ying Chi

Xiansheng Hua

Yubo Guo

Yimin Lu

Manzhou Wang

Bo Li

Yuanyong Lu

Wenjian Xu

Zhao Jiang

Guopeng Sun

Zuliang Chen

Zhao Yang

Zhigen Wang

Shengxiang Jiang

Yongfeng Ran

Zhihong Li

Jie Yan

Jianwen Zhu

Chiwei Joong

The embodiments of the present application provide an instruction retirement unit, an instruction execution unit, and a related apparatus and method. The instruction retirement unit includes: a reception subunit, configured to receive a completion request signal; an arbitration subunit, configured to send a completion permission signal to an instruction execution unit after determining that instructions to be completed can be completed, and store instruction completion information of the instructions to be completed into instruction buffer table entries in a buffer; and a retirement subunit, configured to perform, based on the instruction completion information stored in each of the instruction buffer table entries, retirement processing on instructions that have already been completed and have not been retired, and delete the instruction completion information of retired instructions from the instruction buffer table entries.

Instruction retirement unit, instruction execution unit, processing unit, computing device, and instruction processing method for performing retirement processing on instructions based on instruction completion information

The embodiments of the present application provide a processing unit. The processing unit comprises: an instruction fetching unit configured for fusing instruction of vector configuration instruction and vector operation instruction that are adjacent in order to obtain fusion instruction; an instruction decoding unit configured to decode the fusion instruction to obtain first execution information and second execution information; a vector configuration unit configured to execute the vector configuration instruction according to the first execution information, modify vector control register, and bypass the value of the modified vector control register to the vector operation unit; the vector operation unit configured to execute the vector operation instruction according to the second execution information and the value of the modified vector control register.

Computing device and method for fusing and executing vector instructions

The present application discloses a method, device, and system for processing a medical image. The method includes obtaining a source spinal image, identifying one or more vertebral bodies and one or more intervertebral discs comprised in the source spinal image, determining the vertebral body recognition results corresponding to the one or more vertebral bodies and the intervertebral disc recognition results corresponding to the one or more intervertebral discs, and determining target recognition results corresponding to the source spinal image based at least in part one on one or more of the vertebral body recognition results and the intervertebral disc recognition results.

Processing method, model training method, means, and storage medium for spinal images

An instruction processing apparatus is disclosed and includes: an instruction cache, which maps data blocks in a memory based on a multi-way set-associative structure and includes a plurality of cache lines; and an access control unit, coupled between an instruction fetch unit and the instruction cache, and adapted to read the plurality of cache lines respectively by using a plurality of data channels, and select a hit cache line from the plurality of cache lines by using a plurality of selection channels, to obtain an instruction, where the access control unit includes a path prediction unit, where the path prediction unit obtains, based on a type of the instruction, path prediction information corresponding to an instruction address, and enables at least one data channel and/or at least one selection channel based on the path prediction information. The instruction processing apparatus selectively enables an access channel of the instruction cache based on the path prediction information by using the access control unit, to reduce dynamic power consumption in access. A corresponding path prediction method, a computer system, and a system-on-chip are also disclosed.

Path prediction method used for instruction cache, access control unit, and instruction processing apparatus

An instruction processing device and an instruction processing method are provided. The instruction processing device includes: a first-level branch target buffer, configured to store entries of a first plurality of branch instructions; a second-level branch target buffer, configured to store entries of a second plurality of branch instructions, wherein the entries in the first-level branch target buffer are accessed faster than the entries in the second-level branch target buffer; an instruction fetch unit coupled to the first-level branch target buffer and the second-level branch target buffer, the instruction fetch unit including circuitry configured to add, for a first branch instruction, one or more entries corresponding to the first branch instruction into the first-level branch target buffer when the one or more entries corresponding to the first branch instruction are identified in the second-level branch target buffer; and an execution unit including circuitry configured to execute the first branch instruction.

Moving entries between multiple levels of a branch predictor based on a performance loss resulting from fewer than a pre-set number of instructions being stored in an instruction cache register

An instruction processing device and an instruction processing method are disclosed. The instruction processing device includes: an instruction boundary prediction unit including circuitry configured to acquire an instruction packet of a variable-length instruction set and to add instruction prediction information to a plurality of instruction meta-fields in the instruction packet; and an instruction pipeline structure comprising an instruction fetch unit including an instruction boundary determination unit including circuitry configured to determine instruction boundary information according to the instruction prediction information to obtain one or more instructions in the instruction packet.

System, device, and method for obtaining instructions from a variable-length instruction set

A processor achieving a zero-overhead loop, includes instruction stream control circuitry and loop control circuitry. The loop control circuitry includes loop address detecting circuitry and loop end determining circuitry. By combining instructions and hardware, the loop control circuitry eliminates additional control instructions required b each loop iteration and can achieve loop acceleration with zero overhead, thereby improving the loop execution efficiency.

Processor for executing a loop acceleration instruction to start and end a loop

A graphical structure model trained by using labeled samples is obtained. The graphical structure model is defined based on an enterprise relationship network that includes nodes and edges. Each labeled sample includes a label indicating whether a corresponding node is a risky credit node. The graphical structure model is configured to iteratively calculate an embedding vector of at least one node in a hidden feature space based on an original feature of the at least one node and/or a feature of an edge associated with the at least one node. An embedding vector corresponding to a test-sample is calculated by using the graphical structure model. Credit risk analysis is performed on the test-sample. The credit risk analysis is performed based on a feature of the test-sample represented in the embedding vector. A node corresponding to the test-sample is labeled as a credit risk node.

Graphical structure model-based credit risk control

One or more implementations of the present specification provide risk control of transactions based on a graphical structure model. A graphical structure model trained by using labeled samples is obtained. The graphical structure model is defined based on a transaction data network that includes nodes representing entities in a transaction and edges representing relationships between the entities. Each labeled sample includes a label indicating whether a node corresponding to the labeled sample is a risky transaction node. The graphical structure model is configured to iteratively calculate an embedding vector of the node in a latent feature space based on an original feature of the node or a feature of an edge associated with the node. An embedding vector of an input sample is calculated by using the graphical structure model. Transaction risk control is performed on the input sample based on the embedding vector.

Graphical structure model-based transaction risk control

A processor core, a processor, an apparatus, and an instruction processing method are disclosed. The processor core includes: an instruction fetch unit, where the instruction fetch unit includes a speculative execution predictor and the speculative execution predictor compares a program counter of a memory access instruction with a table entry stored in the speculative execution predictor and marks the memory access instruction; a scheduler unit adapted to adjust a send order of marked memory access instructions and send the marked memory access instructions according to the send order; an execution unit adapted to execute the memory access instructions according to the send order. In the instruction fetch unit, a memory access instruction is marked according to a speculative execution prediction result. In the scheduler unit, a send order of memory access instructions is determined according to the marked memory access instruction and the memory access instructions are sent. In the execution unit, the memory access instructions are executed according to the send order. This helps avoiding re-execution of a memory access instruction due to an address correlation of the memory access instruction. Consequently, this eliminates the need of adding an idle cycle in an instruction pipeline and the need of refreshing the pipeline to clear a memory access instruction that is incorrectly speculated.

Speculative execution of correlated memory access instruction methods, apparatuses and systems

Embodiments of the present disclosure provide an apparatus, comprising: one or more instruction executing circuitries, wherein each instruction executing circuitry of the one or more instruction executing circuitries is configured to execute an instruction of a corresponding instruction type, and an instruction scheduling circuitry that is communicatively coupled to the one or more instruction executing circuitries, the instruction scheduling circuitry is configured to: determine according to an instruction type of the instruction and a number of instructions that have been allocated to the one or more instruction executing circuitries, an instruction executing circuitry from the one or more instruction executing circuitries to schedule the instruction for execution, and allocated the instruction to the determined instruction executing circuitry.

Instruction processing apparatuses, processors, and processing methods

A graphical structure model trained with labeled samples is obtained. The graphical structure model is defined based on an account relationship network that comprises a plurality of nodes and edges. The edges correspond to relationships between adjacent nodes. Each labeled sample comprises a label indicating whether a corresponding node is an abnormal node. The graphical structure model is configured to iteratively calculate, for at least one node of the plurality of nodes, an embedding vector in a hidden feature space based on an original feature of the least one node and/or a feature of an edge associated with the at least one node. A first embedding vector that corresponds to a to-be-tested sample is calculated using the graphical structure model. Abnormal account prevention and control is performed on the to-be-tested sample based on the first embedding vector.

Graphical structure model-based prevention and control of abnormal accounts

An example service addressing method in a distributed environment includes: generating a service querying request, the service querying request including a querying condition; acquiring a first server address list of a target service corresponding to the querying condition; acquiring a failed server address list; deleting the failed server address list from the first server address list to obtain a second server address list; selecting a target server address from the second server address list; and initiating an invocation of the target service to the target server address. The techniques of the present disclosure improve the efficiency of the service invocation.

Service addressing in distributed environment

LED filaments and support

Growing community of inventors

Hangzhou, China

Chen Chen